Datasheet > CY7C1346H

CY7C1346H

更新时间： 2024-11-21 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	710K
描述
2-Mbit (64K x 36) Pipelined Sync SRAM

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CY7C1346H 数据手册

CY7C1346H

2-Mbit (64K x 36) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 64K × 36 common I/O architecture

• 3.3V core power supply

The CY7C1346H SRAM integrates 64K x 36 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

— 3.5 ns (166-MHz device)

Control inputs (

and

ADSC ADSP

), Write Enables

). Asynchronous

ADV

), and Global Write (

BWE

(

, and

BW_[A:D]

• Provide high-performance 3-1-1-1 access rate

inputs include the Output Enable ( ) and the ZZ pin.

• User-selectable burst counter supporting Intel^®

Addresses and chip enables are registered at rising edge of

Pentium^®interleaved or linear burst sequences

clock when either Address Strobe Processor (

) or

ADSP

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address Strobe Controller (

burst addresses can be internally generated as controlled by

the Advance pin ( ).

) are active. Subsequent

ADSC

ADV

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode Option

controlled by the Byte Write control inputs.

when active

causes all bytes to be written.

LOW

The CY7C1346H operates from a +3.3V core power supply

while all outputs also operate with either a +3.3V/2.5V supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

CLR

LOGIC

ADSC

ADSP

DQ^D,DQ

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

D ,DQPD

BYTE

WRITE DRIVER

C ,DQPC

BYTE

WRITE REGISTER

C,DQPC

DQs

OUTPUT

BUFFERS

DQP

OUTPUT

REGISTERS

MEMORY

ARRAY

SENSE

AMPS

DQ^B,DQP

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

DQA,DQP

A ,DQPA

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05672 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 26, 2006

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与CY7C1346H相关器件

型号	品牌	获取价格	描述	数据表
CY7C1346H-133AXC	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-133AXI	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-166AXC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346H-166AXI	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346L-166AC	CYPRESS	获取价格	Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100AC	CYPRESS	获取价格	Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100ACT	CYPRESS	获取价格	Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100AI	ETC	获取价格	x36 Fast Synchronous SRAM
CY7C1347-166AC	CYPRESS	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A	ETC	获取价格	Memory

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