Datasheet > 存储 > SRAM> CY7C1347B-100BGI

CY7C1347B-100BGI

更新时间： 2024-11-21 03:01:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	732K
描述
128K x 36 Synchronous-Pipelined Cache RAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1347B-100BGI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数：	119	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.82	最长访问时间：	5.5 ns
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	长度：	22 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	2.4 mm	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.325 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	14 mm	Base Number Matches：	1

CY7C1347B-100BGI 数据手册

1CY7C1347

CY7C1347B

128K x 36 Synchronous-Pipelined Cache RAM

The CY7C1347B I/O pins can operate at either the 2.5V or the

3.3V level, the I/O pins are 3.3V tolerant when V_DDQ= 2.5V.

Features

• Supports 100-MHz bus for Pentium and PowerPC™

operations with zero wait states

• Fully registered inputs and outputs for pipelined oper-

ation

• 128K by 36 common I/O architecture

• 3.3V core power supply

• 2.5V/3.3V I/O operation

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device).

The CY7C1347B supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can be

initiated by asserting either the Processor Address Strobe

(ADSP) or the Controller Address Strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input. A 2-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

• User-selectable burst counter supporting Intel Pen-

tium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100 TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

• Available in Industrial and Commercial Temperature

ranges

Byte write operations are qualified with the four Byte Write

Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

Functional Description

The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined

cache SRAM designed to support zero-wait-state secondary

cache with minimal glue logic.

MODE

Logic Block Diagram

)

[1;0]

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

128KX36

MEMORY

ARRAY

[16:0]

DQ[31:24], DP[3]

BYTEWRITE

REGISTERS

BWE

DQ[23:16], DP[2]

BYTEWRITE

REGISTERS

DQ[15:8], DP[1]

BYTEWRITE

REGISTERS

DQ[7:0], DP[0]

BYTEWRITE

REGISTERS

ENABLE CE

OUTPUT

INPUT

ENABLE DELAY

REGISTERS

CLK

SLEEP

CONTROL

[31:0]

[3:0]

Pentium and Intel are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 11, 2001

12 3 4 5 6 7...17

中文翻译

下载PDF

与CY7C1347B-100BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1347B-100BGIT	CYPRESS	获取价格	Cache SRAM, 128KX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1347B-133AC	CYPRESS	获取价格	128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347B-133AC	ROCHESTER	获取价格	128KX36 CACHE SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347B-133ACT	CYPRESS	获取价格	Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347B-133ACT	ROCHESTER	获取价格	128KX36 CACHE SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347B-133AI	CYPRESS	获取价格	128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347B-133AIT	CYPRESS	获取价格	Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347B-133BGC	CYPRESS	获取价格	128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347B-133BGCT	CYPRESS	获取价格	Cache SRAM, 128KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1347B-133BGI	CYPRESS	获取价格	128K x 36 Synchronous-Pipelined Cache RAM

与CY7C1347B-100BGI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

31
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

22
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

51
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

50

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1347B-100BGI

CY7C1347B-100BGI 技术参数

CY7C1347B-100BGI 数据手册

与CY7C1347B-100BGI相关器件

与CY7C1347B-100BGI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1347B-100BGI

CY7C1347B-100BGI 技术参数

CY7C1347B-100BGI 数据手册

与CY7C1347B-100BGI相关器件

与CY7C1347B-100BGI相关文章

您还可以找

您在本页遇到什么问题？