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CY7C1346L-166AC

更新时间： 2024-11-21 21:15:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
15页 482K
描述
Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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中文翻译

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CY7C1346L-166AC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.88
Base Number Matches：1

CY7C1346L-166AC 数据手册

 浏览型号CY7C1346L-166AC的Datasheet PDF文件第2页浏览型号CY7C1346L-166AC的Datasheet PDF文件第3页浏览型号CY7C1346L-166AC的Datasheet PDF文件第4页浏览型号CY7C1346L-166AC的Datasheet PDF文件第5页浏览型号CY7C1346L-166AC的Datasheet PDF文件第6页浏览型号CY7C1346L-166AC的Datasheet PDF文件第7页 
fax id: 1112  
PRELIMINARY  
CY7C1346  
64K x 36 Synchronous-Pipelined Cache RAM  
Features  
Functional Description  
• Low (1.65 mW) standby power (f=0, L version)  
The CY7C1346 is a 3.3V 64K by 36 synchronous-pipelined  
cache SRAM designed to support zero wait state secondary  
cache with minimal glue logic.  
• Supports 100-MHz bus for Pentium® and PowerPC™  
operations with zero wait states  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. Max-  
imum access delay from the clock rise is 3.5 ns (166-MHz  
device). A 2-bit on-chip wraparound burst counter captures the  
first address in a burst sequence and automatically increments  
the address for the rest of the burst access.  
• Fully registered inputs and outputs for pipelined  
operation  
• 64K x 36 common I/O architecture  
• Single 3.3V power supply  
• Fast clock-to-output times  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
— 4.5 ns (for 117-MHz device)  
— 5.5 ns (for 100-MHz device)  
The CY7C1346 supports either the interleaved burst se-  
quence used by the Intel Pentium processor or a linear burst  
sequence used by processors such as the PowerPC. The burst  
sequence is selected through the MODE pin. Accesses can be  
initiated by asserting either the processor address strobe  
(ADSP) or the controller address strobe (ADSC) at clock rise.  
Address advancement through the burst sequence is con-  
trolled by the ADV input.  
• User-selectable burst counter supporting Intel®  
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Byte write operations are qualified with the four Byte Write  
Select (BW  
) inputs. A Global Write Enable (GW) overrides  
[3:0]  
• Asynchronous output enable  
the byte write inputs and writes data to all four bytes. All writes  
are conducted with on-chip synchronous self-timed write cir-  
cuitry.  
• JEDEC-standard 100-pin TQFP pinout  
• “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous chip selects (CE , CE , CE ) and an asyn-  
1
2
3
chronous output enable (OE) provide for easy bank selection  
and output three-state control. In order to provide proper data  
during depth expansion, OE is masked during the first clock of  
a read cycle when emerging from a deselected state.  
Logic Block Diagram  
2
(A ,A )  
0
1
Q
0
CLK  
ADV  
ADSC  
BURST  
COUNTER  
CE  
CLR  
Q
1
ADSP  
Q
14  
16  
ADDRESS  
REGISTER  
CE  
D
64K 36  
X
A
[15:0]  
16  
14  
MEMORY  
ARRAY  
GW  
BWE  
DDQ[31:24],DP[3]  
Q
BW  
BYTEWRITE  
3
REGISTERS  
DQ[23:16],DP[2]  
D
D
Q
Q
Q
BW  
2
BYTEWRITE  
REGISTERS  
DQ[15:8],DP[1]  
BW  
BYTEWRITE  
1
REGISTERS  
D
DQ[7:0],DP[0]  
BYTEWRITE  
BW  
0
REGISTERS  
36  
36  
CE  
1
2
CE  
D
ENABLE  
REGISTER  
Q
CE  
CE  
3
CLK  
D
Q
OUTPUT  
REGISTERS  
CLK  
INPUT  
REGISTERS  
CLK  
ENABLE DELAY  
REGISTER  
CLK  
OE  
ZZ  
SLEEP  
CONTROL  
DQ  
DP  
[31:0]  
[3:0]  
Intel and Pentium are registered trademarks of Intel Corporation.  
PowerPC is a trademark of IBM Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
August 24, 1998  
1234567...15

中文翻译

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与CY7C1346L-166AC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1347-100AC CYPRESS

获取价格

 		Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100ACT CYPRESS

获取价格

 		Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100AI ETC

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 		x36 Fast Synchronous SRAM
CY7C1347-166AC CYPRESS

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 		Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A ETC

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 		Memory
CY7C1347A-117AC CYPRESS

获取价格

 		Standard SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-117BGC CYPRESS

获取价格

 		Standard SRAM, 128KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1347A-133AC CYPRESS

获取价格

 		Standard SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-133AC ROCHESTER

获取价格

 		128KX36 STANDARD SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-150AC CYPRESS

获取价格

 		Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10

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