Datasheet > CY7C1347-100AC

CY7C1347-100AC

更新时间： 2024-11-21 21:17:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
15页	482K
描述
Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1347-100AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.78	最长访问时间：	5.5 ns
其他特性：	PIPELINE ARCHITECTURE	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.0025 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.325 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CY7C1347-100AC 数据手册

fax id: 1113

PRELIMINARY

CY7C1347

128K x 36 Synchronous-Pipelined Cache RAM

Features

Functional Description

• Low (1.65 mW) standby power (f=0, L version)

The CY7C1347 is a 3.3V 128K by 36 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

• Supports 100-MHz bus for Pentium® and PowerPC™

operations with zero wait states

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device). A 2-bit on-chip wraparound burst counter captures the

first address in a burst sequence and automatically increments

the address for the rest of the burst access.

• Fully registered inputs and outputs for pipelined

operation

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 117-MHz device)

— 5.5 ns (for 100-MHz device)

The CY7C1347 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can be

initiated by asserting either the processor address strobe

(ADSP) or the controller address strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input.

• User-selectable burst counter supporting Intel®

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Byte write operations are qualified with the four Byte Write

Select (BW

) inputs. A Global Write Enable (GW) overrides

[3:0]

• Asynchronous output enable

the byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

• JEDEC-standard 100-pin TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous chip selects (CE , CE , CE ) and an asyn-

chronous output enable (OE) provide for easy bank selection

and output three-state control. In order to provide proper data

during depth expansion, OE is masked during the first clock of

a read cycle when emerging from a deselected state.

Logic Block Diagram

(A ,A )

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

128K x 36

[15:0]

MEMORY

ARRAY

BWE

DDQ[31:24]

BYTEWRITE

REGISTERS

DQ[23:16]

BYTEWRITE

REGISTERS

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

OUTPUT

INPUT

REGISTERS

CLK

ENABLE DELAY

CLK

REGISTERS

CLK

SLEEP

CONTROL

[31:0]

[3:0]

Intel and Pentium are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 24, 1998

12 3 4 5 6 7...15

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与CY7C1347-100AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1347-100ACT	CYPRESS	获取价格	Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100AI	ETC	获取价格	x36 Fast Synchronous SRAM
CY7C1347-166AC	CYPRESS	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A	ETC	获取价格	Memory
CY7C1347A-117AC	CYPRESS	获取价格	Standard SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-117BGC	CYPRESS	获取价格	Standard SRAM, 128KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1347A-133AC	CYPRESS	获取价格	Standard SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-133AC	ROCHESTER	获取价格	128KX36 STANDARD SRAM, 4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347A-150AC	CYPRESS	获取价格	Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
CY7C1347A-166AC	CYPRESS	获取价格	Standard SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10

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