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CY7C1346F-133ACT PDF预览

CY7C1346F-133ACT

更新时间： 2024-11-21 19:44:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
16页 341K
描述
Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1346F-133ACT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.64
最长访问时间：4 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：2359296 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1346F-133ACT 数据手册

 浏览型号CY7C1346F-133ACT的Datasheet PDF文件第2页浏览型号CY7C1346F-133ACT的Datasheet PDF文件第3页浏览型号CY7C1346F-133ACT的Datasheet PDF文件第4页浏览型号CY7C1346F-133ACT的Datasheet PDF文件第5页浏览型号CY7C1346F-133ACT的Datasheet PDF文件第6页浏览型号CY7C1346F-133ACT的Datasheet PDF文件第7页 
CY7C1346F  
2-Mbit (64K x 36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• 64K × 36 common I/O architecture  
• 3.3V core power supply  
• 3.3V I/O operation  
• Fast clock-to-output times  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
— 4.5 ns (for 100-MHz device)  
The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells  
with advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
and  
ADSC ADSP  
), Write Enables  
ADV  
(
, and  
), and Global Write (  
BWE  
). Asynchronous  
GW  
BW[A:D]  
inputs include the Output Enable ( ) and the ZZ pin.  
OE  
Addresses and chip enables are registered at rising edge of  
• Provide high-performance 3-1-1-1 access rate  
clock when either Address Strobe Processor (  
) or  
ADSP  
• User-selectable burst counter supporting Intel  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
Pentiuminterleaved or linear burst sequences  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• Offered in JEDEC-standard 100-pin TQFP package  
• “ZZ” Sleep Mode Option  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
controlled by the Byte Write control inputs.  
when active  
GW  
causes all bytes to be written.  
LOW  
The CY7C1346F operates from a +3.3V core power supply  
while all outputs also operate with a +3.3V supply. All inputs  
and outputs are JEDEC-standard JESD8-5-compatible.  
Logic Block Diagram  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER  
AND  
CLR  
Q0  
LOGIC  
ADSC  
ADSP  
DQD,DQ  
BYTE  
WRITE REGISTER  
D
DQ  
BYTE  
WRITE DRIVER  
D ,DQPD  
BW  
D
DQ  
BYTE  
WRITE DRIVER  
C ,DQPC  
DQ  
BYTE  
WRITE REGISTER  
C,DQPC  
DQs  
DQP  
DQP  
BW  
C
OUTPUT  
BUFFERS  
A
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
SENSE  
AMPS  
B
C
DQB,DQP  
B
E
DQB,DQP  
B
DQP  
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BW  
BW  
B
A
DQP  
D
DQA,DQP  
A
DQ  
A ,DQPA  
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
1
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05384 Rev. *B  
Revised December 3, 2004  
1234567...16

中文翻译

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CY7C1346F-133ACT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1346H-166AXC CYPRESS

功能相似

 2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-166AC CYPRESS

功能相似

 2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-100AC CYPRESS

功能相似

 2-Mbit (64K x 36) Pipelined Sync SRAM

与CY7C1346F-133ACT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1346F-166AC CYPRESS

获取价格

 		2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-166ACT CYPRESS

获取价格

 		Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346H CYPRESS

获取价格

 		2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346H-133AXC CYPRESS

获取价格

 		Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-133AXI CYPRESS

获取价格

 		Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-166AXC CYPRESS

获取价格

 		2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346H-166AXI CYPRESS

获取价格

 		2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346L-166AC CYPRESS

获取价格

 		Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100AC CYPRESS

获取价格

 		Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1347-100ACT CYPRESS

获取价格

 		Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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