Datasheet > CY7C1346A-117AC

CY7C1346A-117AC

更新时间： 2024-11-21 18:13:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
13页	162K
描述
Standard SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1346A-117AC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
最长访问时间：	4 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	117 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	2359296 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.002 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.35 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

CY7C1346A-117AC 数据手册

346A

PRELIMINARY

CY7C1346A/GVT7164D36

64K x 36 Synchronous Pipelined Burst SRAM

The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36

SRAM cells with advanced synchronous peripheral circuitry

Features

• Fast access times: 3.5, 3.8, and 4.0 ns

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a positive-

edge-triggered clock input (CLK). The synchronous inputs in-

clude all addresses, all data inputs, address-pipelining Chip

Enable (CE), depth-expansion Chip Enables (CE2 and CE2),

Burst Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW1, BW2, BW3, BW4, and BWE), and Global Write (GW).

• Fast clock speed: 166, 150, 133, and 117 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 3.5 ns and 3.8 ns

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% power supply

• Separate isolated output buffer supply compatible with

3.3V and 2.5V I/O (V_CCQ): 2.375V to 3.6V

Asynchronous inputs include the Output Enable (OE), Burst

Mode Control (MODE), and sleep mode control (ZZ). The data

outputs (Q), enabled by OE, are also asynchronous.

• 5V tolerant inputs except I/Os

Addresses and chip enables are registered with either address

status processor (ADSP) or Address Status Controller (ADSC)

input pins. Subsequent burst addresses can be internally gen-

erated as controlled by the Burst Advance pin (ADV).

• Clamp diodes to V_SSQat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

pipeline

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual byte write allows individual byte to be written. BW1 con-

trols DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and

DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls

DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be

active only with BWE being LOW. GW being LOW causes all

bytes to be written.

The CY7C1346A/GVT7164D36 operates from a +3.3V power

supply. All inputs and outputs are TTL-compatible. The device

is ideally suited for 486, Pentium®, 680x0, and PowerPC™

systems and for systems that are benefited from a wide syn-

chronous data bus.

Functional Description

The Cypress Synchronous Burst SRAM family employs high-

speed, low-power CMOS designs using advanced triple-layer

polysilicon, double-layer metal technology. Each memory cell

consists of four transistors and two high-valued resistors.

Selection Guide

7C1346A-166

7164D36-3

7C1346A-150

7164D36-4

7C1346A-133

7164D36-5

7C1346A1-117

7164D36-6

Maximum Access Time (ns)

3.5

425

3.8

400

4.0

375

4.0

350

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Pentium is a registered trademark of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05156 Rev. **

Revised September 6, 2001

12 3 4 5 6 7...13

中文翻译

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与CY7C1346A-117AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1346A-133AC	CYPRESS	获取价格	Standard SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346A-166AC	CYPRESS	获取价格	Standard SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346F	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-100AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-100ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346F-133AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-133ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346F-166AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-166ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346H	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM

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