Datasheet > CY7C1303BV25_12

CY7C1303BV25_12

更新时间： 2024-11-01 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
25页	412K
描述
18-Mbit Burst of Two-Pipelined SRAM with QDRÂ® Architecture

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CY7C1303BV25_12 数据手册

CY7C1303BV25

18-Mbit Burst of Two-Pipelined SRAM

with QDR^®Architecture

18-Mbit Burst of Two-Pipelined SRAM with QDR^®Architecture

Features

Functional Description

■ Separate independent read and write data ports

❐ Supports concurrent transactions

The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM

equipped with QDR^®architecture. QDR architecture consists of

two separate ports to access the memory array. The read port

has dedicated data outputs to support read operations and the

write port has dedicated data inputs to support write operations.

Access to each port is accomplished through a common address

bus. The Read address is latched on the rising edge of the K

■ 167 MHz clock for high bandwidth

❐ 2.5 ns clock-to-valid access time

■ Two word burst on all accesses

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 333 MHz) at 167 MHz

clock and the Write address is latched on the rising edge of K

clock. QDR has separate data inputs and data outputs to

completely eliminate the need to “turn around” the data bus

required with common I/O devices. Accesses to the

CY7C1303BV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock (K).

In order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces.

Therefore, data can be transferred into the device on every rising

edge of both input clocks (K and K) and out of the device on every

rising edge of the output clock (C and C, or K and K when in

single clock mode) thereby maximizing performance while

simplifying system design. Each address location is associated

with two 18-bit words (CY7C1303BV25) that burst sequentially

into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches.

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ 2.5 V core power supply with HSTL inputs and outputs

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Variable drive HSTL output buffers

Depth expansion is accomplished with a port select input for

each port. Each Port Selects allow each port to operate

independently.

■ Expanded HSTL output voltage (1.4 V to 1.9 V)

■ JTAG Interface

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Variable Impedance HSTL

Configurations

CY7C1303BV25 – 1 M × 18

Selection Guide

Description

Maximum operating frequency

CY7C1303BV25-167 Unit

167

500

MHz

Maximum operating current

Cypress Semiconductor Corporation

Document Number: 38-05627 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 24, 2012

12 3 4 5 6 7...25

中文翻译

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与CY7C1303BV25_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1303BV25-133BZC	CYPRESS	获取价格	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1303BV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZXC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZXI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303CV25	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZXC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZXI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture

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