Datasheet > CY7C1303BV25-133BZC

CY7C1303BV25-133BZC

更新时间： 2024-10-31 19:43:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
19页	247K
描述
QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165

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CY7C1303BV25-133BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.88
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.5/1.8,2.5 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	2.4 V	子类别：	SRAMs
最大供电电压 (Vsup)：	2.6 V	最小供电电压 (Vsup)：	2.4 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

CY7C1303BV25-133BZC 数据手册

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CY7C1303BV25

CY7C1306BV25

PRELIMINARY

18-Mbit Burst of 2 Pipelined SRAM with

QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

The CY7C1303BV25 and CY7C1306BV25 are 2.5V

Synchronous Pipelined SRAMs equipped with QDR™ archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Accesses to the CY7C1303BV25/

CY7C1306BV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K) and out of the

device on every rising edge of the output clock (C and C, or K

and K when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303BV25) or two

36-bit words (CY7C1306BV25) that burst sequentially into or

out of the device.

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix) Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently. 38-05627

• Variable Impedance HSTL

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1303BV25 – 1M x 18

CY7C1306BV25 – 512K x 36

Cypress Semiconductor Corporation

Document #: 38-05627 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 29, 2004

12 3 4 5 6 7...19

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与CY7C1303BV25-133BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1303BV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZXC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303BV25-167BZXI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A
CY7C1303CV25	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZXC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303CV25-167BZXI	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1303V25	ETC	获取价格	Memory

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