Datasheet > CY7C1215H

CY7C1215H

更新时间： 2024-11-07 04:35:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	381K
描述
1-Mbit (32K x 32) Pipelined Sync SRAM

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CY7C1215H 数据手册

CY7C1215H

1-Mbit (32K x 32) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 32K × 32 common I/O architecture

The CY7C1215H SRAM integrates 32K x 32 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode Option

The CY7C1215H operates from a +3.3V core power supply

while all outputs may operate either with a + 2.5V or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

CLR

LOGIC

ADSC

ADSP

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

BYTE

OUTPUT

BUFFERS

WRITE DRIVER

OUTPUT

REGISTERS

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

DQ s

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05666 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 5, 2006

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与CY7C1215H相关器件

型号	品牌	获取价格	描述	数据表
CY7C1215H-100AXC	CYPRESS	获取价格	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1215H-100AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1215H-133AXC	CYPRESS	获取价格	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1215H-133AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1215H-166AXC	CYPRESS	获取价格	Cache SRAM, 32KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, T
CY7C1215H-166AXI	CYPRESS	获取价格	Cache SRAM, 32KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, T
CY7C1217F	CYPRESS	获取价格	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217F-100AC	CYPRESS	获取价格	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217F-100ACT	CYPRESS	获取价格	Cache SRAM, 32KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1217H	CYPRESS	获取价格	1-Mbit (32K x 36) Flow-Through Sync SRAM

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