CY7C1218F
1-Mb (32K x36) Pipelined Sync SRAM
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Features
• Registered inputs and outputs for pipelined operation
• 32K × 36 common I/O architecture
• 3.3V core power supply
• 3.3V I/O operation
• Fast clock-to-output times
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
Control inputs (
,
,
and
), Write Enables
ADV
ADSC ADSP
(
, and ), and Global Write (
BWE
). Asynchronous
GW
BW[A:D]
inputs include the Output Enable ( ) and the ZZ pin.
OE
Addresses and chip enables are registered at rising edge of
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
• Provide high-performance 3-1-1-1 access rate
ADV
• User-selectable burst counter supporting Intel
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP package
• “ZZ” Sleep Mode Option
Functional Description[1]
controlled by the Byte Write control inputs.
when active
GW
causes all bytes to be written.
LOW
The CY7C1218F operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
The CY7C1218F SRAM integrates 32,768 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQD,DQ
BYTE
WRITE REGISTER
D
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQ
BYTE
WRITE DRIVER
C ,DQPC
DQ
BYTE
WRITE REGISTER
C,DQPC
DQs
DQP
DQP
BW
C
OUTPUT
BUFFERS
A
OUTPUT
REGISTERS
MEMORY
ARRAY
SENSE
AMPS
B
C
DQB,DQP
B
E
DQB,DQP
B
DQP
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BW
BW
B
A
DQP
D
DQA,DQP
A
DQ
A ,DQPA
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05422 Rev. **
Revised January 26, 2004