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CY7C1217F-100ACT PDF预览

CY7C1217F-100ACT

更新时间： 2024-11-09 13:01:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
14页 322K
描述
Cache SRAM, 32KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1217F-100ACT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.6
最长访问时间：8 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：1179648 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1217F-100ACT 数据手册

 浏览型号CY7C1217F-100ACT的Datasheet PDF文件第2页浏览型号CY7C1217F-100ACT的Datasheet PDF文件第3页浏览型号CY7C1217F-100ACT的Datasheet PDF文件第4页浏览型号CY7C1217F-100ACT的Datasheet PDF文件第5页浏览型号CY7C1217F-100ACT的Datasheet PDF文件第6页浏览型号CY7C1217F-100ACT的Datasheet PDF文件第7页 
CY7C1217F  
1-Mbit (32K x 36) Flow-Through Sync SRAM  
7.5 ns (117-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Features  
• 32K x 36 common I/O  
• 3.3V –5% and +10% core power supply (VDD  
• 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 7.5 ns (117-MHz version)  
— 8.0 ns (100-MHz version)  
)
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
)
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
), Write Enables  
). Asynchronous  
and  
ADV  
ADSC ADSP  
(
,
and  
), and Global Write (  
BW[A:D]  
BWE  
GW  
(
)
and the ZZ pin  
.
nputs include the Output Enable  
OE  
i
• Provide high-performance 2-1-1-1 access rate  
The CY7C1217F allows either interleaved or linear burst  
sequences, selected by the MODE input pin. A HIGH selects  
an interleaved burst sequence, while a LOW selects a linear  
burst sequence. Burst accesses can be initiated with the  
Processor Address Strobe (ADSP) or the cache Controller  
Address Strobe (ADSC) inputs. Address advancement is  
controlled by the Address Advancement (ADV) input.  
• User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
• Supports 3.3V I/O level  
• Offered in JEDEC-standard 100-pin TQFP  
• “ZZ” Sleep Mode option  
Functional Description[1]  
The CY7C1217F is a 32,768 x 36 synchronous cache RAM  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1217F operates from a +3.3V core power supply  
while all outputs may operate with a +3.3V supply. All inputs  
and outputs are JEDEC-standard JESD8-5-compatible.  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A[1:0]  
MODE  
ADV  
CLK  
Q1  
BURST  
COUNTER  
AND LOGIC  
Q0  
CLR  
ADSC  
ADSP  
DQ  
BYTE  
WRITE REGISTER  
D, DQPD  
DQ  
BYTE  
WRITE REGISTER  
D, DQPD  
BW  
D
DQ  
BYTE  
WRITE REGISTER  
C, DQPC  
DQ  
BYTE  
WRITE REGISTER  
C, DQPC  
BW  
C
OUTPUT  
BUFFERS  
DQs  
MEMORY  
ARRAY  
SENSE  
AMPS  
DQP  
DQP  
DQP  
A
DQ  
BYTE  
WRITE REGISTER  
B, DQPB  
B
C
DQ  
BYTE  
WRITE REGISTER  
B, DQPB  
BW  
B
DQPD  
DQ  
BYTE  
WRITE REGISTER  
A, DQPA  
DQ  
A, DQPA  
BW  
A
BYTE  
BWE  
WRITE REGISTER  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
CE1  
CE2  
CE3  
OE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05430 Rev. *A  
Revised April 6, 2004  
1234567...14

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