5秒后页面跳转
CY7C109D PDF预览

CY7C109D

更新时间: 2024-11-24 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 990K
描述
1-Mbit (128K x 8) Static RAM

CY7C109D 数据手册

 浏览型号CY7C109D的Datasheet PDF文件第2页浏览型号CY7C109D的Datasheet PDF文件第3页浏览型号CY7C109D的Datasheet PDF文件第4页浏览型号CY7C109D的Datasheet PDF文件第5页浏览型号CY7C109D的Datasheet PDF文件第6页浏览型号CY7C109D的Datasheet PDF文件第7页 
CY7C109D  
CY7C1009D  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description [1]  
• Pin- and function-compatible with CY7C109B/CY7C1009B  
• High speed  
The CY7C109D/CY7C1009D is a high-performance CMOS  
static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE1), an active HIGH Chip Enable (CE2), an active LOW  
Output Enable (OE), and tri-state drivers.The eight input and  
output pins (IO0 through IO7) are placed in a high-impedance  
state when:  
— tAA = 10 ns  
• Low active power  
— ICC = 80 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 3 mA  
• Deselected (CE1 HIGH or CE2 LOW),  
• Outputs are disabled (OE HIGH),  
• 2.0V Data Retention  
• When the write operation is active (CE1 LOW, CE2 HIGH,  
and WE LOW)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2 and OE options  
Write to the device by taking Chip Enable One (CE1) and Write  
Enable (WE) inputs LOW and Chip Enable Two (CE2) input  
HIGH. Data on the eight IO pins (IO0 through IO7) is then  
written into the location specified on the address pins (A0  
through A16).  
• CY7C109DavailableinPb-free32-pin400-MilwideMolded  
SOJ and 32-pin TSOP I packages. CY7C1009D available  
in Pb-free 32-pin 300-Mil wide Molded SOJ package  
Read from the device by taking Chip Enable One (CE1) and  
Output Enable (OE) LOW while forcing Write Enable (WE) and  
Chip Enable Two (CE2) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
appears on the IO pins.  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
IO  
1
A
0
A
1
IO  
2
A
2
128K x 8  
ARRAY  
A
A
A
A
A
A
IO  
3
3
4
5
6
7
8
IO  
4
IO  
5
IO  
6
IO  
POWER  
DOWN  
7
CE  
CE  
COLUMN DECODER  
1
2
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05468 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 22, 2007  
[+] Feedback  

与CY7C109D相关器件

型号 品牌 获取价格 描述 数据表
CY7C109D_11 CYPRESS

获取价格

1-Mbit (128 K × 8) Static RAM Low active powe
CY7C109D-10VXI CYPRESS

获取价格

1-Mbit (128K x 8) Static RAM
CY7C109D-10VXI INFINEON

获取价格

Asynchronous SRAM
CY7C109D-10VXIT INFINEON

获取价格

Asynchronous SRAM
CY7C109D-10ZXC CYPRESS

获取价格

暂无描述
CY7C109D-10ZXI CYPRESS

获取价格

1-Mbit (128K x 8) Static RAM
CY7C109D-10ZXI INFINEON

获取价格

Asynchronous SRAM
CY7C109D-10ZXIT CYPRESS

获取价格

Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY7C109D-10ZXIT INFINEON

获取价格

Asynchronous SRAM
CY7C109D-12VXC CYPRESS

获取价格

Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32