Datasheet > CY7C109D

CY7C109D

更新时间： 2024-11-05 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	990K
描述
1-Mbit (128K x 8) Static RAM

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数据手册

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CY7C109D 数据手册

CY7C109D

CY7C1009D

1-Mbit (128K x 8) Static RAM

Features

Functional Description ^[1]

• Pin- and function-compatible with CY7C109B/CY7C1009B

• High speed

The CY7C109D/CY7C1009D is a high-performance CMOS

static RAM organized as 131,072 words by 8 bits. Easy

memory expansion is provided by an active LOW Chip Enable

(CE₁), an active HIGH Chip Enable (CE₂), an active LOW

Output Enable (OE), and tri-state drivers.The eight input and

output pins (IO₀through IO₇) are placed in a high-impedance

state when:

— t_AA= 10 ns

• Low active power

— I_CC= 80 mA @ 10 ns

• Low CMOS standby power

— I_SB2= 3 mA

• Deselected (CE₁HIGH or CE₂LOW),

• Outputs are disabled (OE HIGH),

• 2.0V Data Retention

• When the write operation is active (CE₁LOW, CE₂HIGH,

and WE LOW)

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE₁, CE₂and OE options

Write to the device by taking Chip Enable One (CE₁) and Write

Enable (WE) inputs LOW and Chip Enable Two (CE₂) input

HIGH. Data on the eight IO pins (IO₀through IO₇) is then

written into the location specified on the address pins (A₀

through A₁₆).

• CY7C109DavailableinPb-free32-pin400-MilwideMolded

SOJ and 32-pin TSOP I packages. CY7C1009D available

in Pb-free 32-pin 300-Mil wide Molded SOJ package

Read from the device by taking Chip Enable One (CE₁) and

Output Enable (OE) LOW while forcing Write Enable (WE) and

Chip Enable Two (CE₂) HIGH. Under these conditions, the

contents of the memory location specified by the address pins

appears on the IO pins.

Logic Block Diagram

INPUT BUFFER

128K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05468 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 22, 2007

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与CY7C109D相关器件

型号	品牌	获取价格	描述	数据表
CY7C109D_11	CYPRESS	获取价格	1-Mbit (128 K × 8) Static RAM Low active powe
CY7C109D-10VXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C109D-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-10ZXC	CYPRESS	获取价格	暂无描述
CY7C109D-10ZXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C109D-10ZXI	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-10ZXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY7C109D-10ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-12VXC	CYPRESS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32