CY7C109D-10ZXC

更新时间： 2024-11-05 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	378K
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CY7C109D-10ZXC 数据手册

CY7C109D

CY7C1009D

1-Mbit (128 K × 8) Static RAM

Features

Functional Description ^[1]

■ Pin- and function-compatible with CY7C109B/CY7C1009B

The CY7C109D/CY7C1009D is a high-performance CMOS

static RAM organized as 131,072 words by 8 bits. Easy

memory expansion is provided by an active LOW Chip Enable

(CE₁), an active HIGH Chip Enable (CE₂), an active LOW

Output Enable (OE), and tri-state drivers.The eight input and

output pins (I/O₀through I/O₇) are placed in a high-impedance

state when:

■ High speed

❐ t_AA= 10 ns

■ Low active power

❐ I_CC= 80 mA at 10 ns

■ Low CMOS standby power

❐ I_SB2= 3 mA

■ Deselected (CE₁HIGH or CE₂LOW),

■ Outputs are disabled (OE HIGH),

■ 2.0 V Data Retention

■ Automatic power-down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE₁, CE₂and OE options

■ When the write operation is active (CE₁LOW, CE₂HIGH,

and WE LOW)

Write to the device by taking Chip Enable One (CE₁) and Write

Enable (WE) inputs LOW and Chip Enable Two (CE₂) input

HIGH. Data on the eight I/O pins (I/O₀through I/O₇) is then

written into the location specified on the address pins (A₀

through A₁₆).

■ CY7C109D available in Pb-free 32-pin 400-Mil wide Molded

SOJ and 32-pin TSOP I packages. CY7C1009D available in

Pb-free 32-pin 300-Mil wide Molded SOJ package

Read from the device by taking Chip Enable One (CE₁) and

Output Enable (OE) LOW while forcing Write Enable (WE) and

Chip Enable Two (CE₂) HIGH. Under these conditions, the

contents of the memory location specified by the address pins

appears on the I/O pins.

Logic Block Diagram

INPUT BUFFER

128K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05468 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 15, 2011

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与CY7C109D-10ZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C109D-10ZXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C109D-10ZXI	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-10ZXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY7C109D-10ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C109D-12VXC	CYPRESS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32
CY7C109D-12VXI	CYPRESS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32
CY7C109D-12ZXC	CYPRESS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY7C109L-15VI	CYPRESS	获取价格	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
CY7C109V33-12VC	CYPRESS	获取价格	128K x 8 Static RAM
CY7C109V33-12ZC	CYPRESS	获取价格	128K x 8 Static RAM

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