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CY7C109D-10ZXI PDF预览

CY7C109D-10ZXI

更新时间: 2024-11-20 02:51:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 990K
描述
1-Mbit (128K x 8) Static RAM

CY7C109D-10ZXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSOP1
包装说明:TSOP1, TSSOP32,.8,20针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:1.9最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e4长度:18.4 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.003 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:8 mmBase Number Matches:1

CY7C109D-10ZXI 数据手册

 浏览型号CY7C109D-10ZXI的Datasheet PDF文件第2页浏览型号CY7C109D-10ZXI的Datasheet PDF文件第3页浏览型号CY7C109D-10ZXI的Datasheet PDF文件第4页浏览型号CY7C109D-10ZXI的Datasheet PDF文件第5页浏览型号CY7C109D-10ZXI的Datasheet PDF文件第6页浏览型号CY7C109D-10ZXI的Datasheet PDF文件第7页 
CY7C109D  
CY7C1009D  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description [1]  
• Pin- and function-compatible with CY7C109B/CY7C1009B  
• High speed  
The CY7C109D/CY7C1009D is a high-performance CMOS  
static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE1), an active HIGH Chip Enable (CE2), an active LOW  
Output Enable (OE), and tri-state drivers.The eight input and  
output pins (IO0 through IO7) are placed in a high-impedance  
state when:  
— tAA = 10 ns  
• Low active power  
— ICC = 80 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 3 mA  
• Deselected (CE1 HIGH or CE2 LOW),  
• Outputs are disabled (OE HIGH),  
• 2.0V Data Retention  
• When the write operation is active (CE1 LOW, CE2 HIGH,  
and WE LOW)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2 and OE options  
Write to the device by taking Chip Enable One (CE1) and Write  
Enable (WE) inputs LOW and Chip Enable Two (CE2) input  
HIGH. Data on the eight IO pins (IO0 through IO7) is then  
written into the location specified on the address pins (A0  
through A16).  
• CY7C109DavailableinPb-free32-pin400-MilwideMolded  
SOJ and 32-pin TSOP I packages. CY7C1009D available  
in Pb-free 32-pin 300-Mil wide Molded SOJ package  
Read from the device by taking Chip Enable One (CE1) and  
Output Enable (OE) LOW while forcing Write Enable (WE) and  
Chip Enable Two (CE2) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
appears on the IO pins.  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
IO  
1
A
0
A
1
IO  
2
A
2
128K x 8  
ARRAY  
A
A
A
A
A
A
IO  
3
3
4
5
6
7
8
IO  
4
IO  
5
IO  
6
IO  
POWER  
DOWN  
7
CE  
CE  
COLUMN DECODER  
1
2
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05468 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 22, 2007  
[+] Feedback  

CY7C109D-10ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C109D-10ZXIT CYPRESS

完全替代

Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
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