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CY7C109D-10ZXI PDF预览

CY7C109D-10ZXI

更新时间: 2024-11-21 14:56:03
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
16页 876K
描述
Asynchronous SRAM

CY7C109D-10ZXI 数据手册

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CY7C109D  
CY7C1009D  
1-Mbit (128 K × 8) Static RAM  
1-Mbit (128  
K × 8) Static RAM  
(OE), and tri-state drivers.The eight input and output pins (I/O0  
through I/O7) are placed in a high-impedance state when:  
Features  
Pin- and function-compatible with CY7C109B/CY7C1009B  
Deselected (CE1 HIGH or CE2 LOW),  
Outputs are disabled (OE HIGH),  
High speed  
tAA = 10 ns  
When the write operation is active (CE1 LOW, CE2 HIGH, and  
WE LOW)  
Low active power  
ICC = 80 mA at 10 ns  
Write to the device by taking Chip Enable One (CE1) and Write  
Enable (WE) inputs LOW and Chip Enable Two (CE2) input  
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then  
written into the location specified on the address pins (A0 through  
Low CMOS standby power  
ISB2 = 3 mA  
2.0 V Data Retention  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
Easy memory expansion with CE1, CE2 and OE options  
A16).  
Read from the device by taking Chip Enable One (CE1) and  
Output Enable (OE) LOW while forcing Write Enable (WE) and  
Chip Enable Two (CE2) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
appears on the I/O pins.  
CY7C109D available in Pb-free 32-pin 400-Mil wide Molded  
SOJ and 32-pin TSOP I packages. CY7C1009D available in  
Pb-free 32-pin 300-Mil wide Molded SOJ package  
The CY7C109D/CY7C1009D device is suitable for interfacing  
with processors that have TTL I/P levels. It is not suitable for  
processors that require CMOS I/P levels. Please see Electrical  
Characteristics on page 4 for more details and suggested  
alternatives.  
Functional Description  
[1]  
The CY7C109D/CY7C1009D  
is a high-performance CMOS  
static RAM organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE1), an  
active HIGH Chip Enable (CE2), an active LOW Output Enable  
For a complete list of related documentation, click here.  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
IO  
1
A
0
A
1
IO  
2
A
2
128K x 8  
ARRAY  
A
A
A
A
A
A
IO  
3
3
4
5
6
7
8
IO  
4
IO  
5
IO  
6
IO  
POWER  
DOWN  
7
CE  
CE  
COLUMN DECODER  
1
2
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 38-05468 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 16, 2015  

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