5秒后页面跳转
CY7C106BN_06 PDF预览

CY7C106BN_06

更新时间: 2024-11-30 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 350K
描述
256K x 4 Static RAM

CY7C106BN_06 数据手册

 浏览型号CY7C106BN_06的Datasheet PDF文件第2页浏览型号CY7C106BN_06的Datasheet PDF文件第3页浏览型号CY7C106BN_06的Datasheet PDF文件第4页浏览型号CY7C106BN_06的Datasheet PDF文件第5页浏览型号CY7C106BN_06的Datasheet PDF文件第6页浏览型号CY7C106BN_06的Datasheet PDF文件第7页 
CY7C106BN  
CY7C1006BN  
256K x 4 Static RAM  
Features  
Functional Description  
The CY7C106BN and CY7C1006BN are high-performance  
CMOS static RAMs organized as 262,144 words by 4 bits.  
Easy memory expansion is provided by an active LOW Chip  
Enable (CE), an active LOW Output Enable (OE), and  
three-state drivers. These devices have an automatic  
power-down feature that reduces power consumption by more  
than 65% when the devices are deselected.  
• High speed  
— tAA = 15 ns  
• CMOS for optimum speed/power  
• Low active power  
— 495 mW  
• Low standby power  
— 275 mW  
Writing to the devices is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O  
pins (I/O0 through I/O3) is then written into the location  
specified on the address pins (A0 through A17).  
• 2.0V data retention (optional)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
Reading from the devices is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the four I/O pins.  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the devices are deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE and WE LOW).  
The CY7C106BN is available in a standard 400-mil-wide SOJ;  
the CY7C1006BN is available in a standard 300-mil-wide SOJ.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
28  
27  
26  
1
2
3
4
5
6
A
1
V
CC  
0
A
A
17  
A
A
15  
2
16  
A
25  
24  
A
3
A
A
4
14  
23  
22  
A
A
5
13  
A
A
12  
7
8
9
10  
11  
12  
13  
6
21  
20  
19  
18  
17  
A
A
7
11  
INPUTBUFFER  
A
NC  
I/O  
8
A
9
10  
3
2
1
A
1
A
I/O  
I/O  
I/O  
A
I/O  
I/O  
I/O  
I/O  
2
3
CE  
A
16  
15  
3
OE  
0
14  
A
GND  
WE  
4
2
1
0
A
5
512 x 512 x 4  
ARRAY  
A
6
A
7
A
8
A
9
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-06429 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 1, 2006  

与CY7C106BN_06相关器件

型号 品牌 获取价格 描述 数据表
CY7C106BN_11 CYPRESS

获取价格

256K x 4 Static RAM
CY7C106BN-15VC CYPRESS

获取价格

256K x 4 Static RAM
CY7C106BN-15VCT CYPRESS

获取价格

Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
CY7C106BN-20VC CYPRESS

获取价格

256K x 4 Static RAM
CY7C106BN-20VCT CYPRESS

获取价格

Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
CY7C106D CYPRESS

获取价格

1-Mbit (256K x 4) Static RAM
CY7C106D-10VXC CYPRESS

获取价格

Standard SRAM, 256KX4, 10ns, CMOS, PDSO28, 0.400 INCH, LEAD FREE, SOJ-28
CY7C106D-10VXI CYPRESS

获取价格

1-Mbit (256K x 4) Static RAM
CY7C106D-10VXIT CYPRESS

获取价格

暂无描述
CY7C106D-12VXC CYPRESS

获取价格

Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.400 INCH, LEAD FREE, SOJ-28