CY7C106BN
CY7C1006BN
256K x 4 Static RAM
Features
Functional Description
The CY7C106BN and CY7C1006BN are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when the devices are deselected.
• High speed
— tAA = 15 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 275 mW
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location
specified on the address pins (A0 through A17).
• 2.0V data retention (optional)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106BN is available in a standard 400-mil-wide SOJ;
the CY7C1006BN is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
28
27
26
1
2
3
4
5
6
A
1
V
CC
0
A
A
17
A
A
15
2
16
A
25
24
A
3
A
A
4
14
23
22
A
A
5
13
A
A
12
7
8
9
10
11
12
13
6
21
20
19
18
17
A
A
7
11
INPUTBUFFER
A
NC
I/O
8
A
9
10
3
2
1
A
1
A
I/O
I/O
I/O
A
I/O
I/O
I/O
I/O
2
3
CE
A
16
15
3
OE
0
14
A
GND
WE
4
2
1
0
A
5
512 x 512 x 4
ARRAY
A
6
A
7
A
8
A
9
POWER
DOWN
COLUMN
DECODER
CE
WE
OE
Cypress Semiconductor Corporation
Document #: 001-06429 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006