Datasheet > CY7C106D

CY7C106D

更新时间： 2024-11-30 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	900K
描述
1-Mbit (256K x 4) Static RAM

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CY7C106D 数据手册

CY7C106D

CY7C1006D

1-Mbit (256K x 4) Static RAM

Features

Functional Description ^[1]

• Pin- and function-compatible with CY7C106B/CY7C1006B

• High speed

The CY7C106D and CY7C1006D are high-performance

CMOS static RAMs organized as 262,144 words by 4 bits.

Easy memory expansion is provided by an active LOW Chip

Enable (CE), an active LOW Output Enable (OE), and tri-state

drivers. These devices have an automatic power-down feature

that reduces power consumption by more than 65% when the

devices are deselected. The four input and output pins (IO₀

through IO₃) are placed in a high-impedance state when:

— t_AA= 10 ns

• Low active power

— I_CC= 80 mA @ 10 ns

• Low CMOS standby power

— I_SB2= 3.0 mA

• Deselected (CE HIGH)

• 2.0V Data Retention

• Outputs are disabled (OE HIGH)

• Automatic power-down when deselected

• CMOS for optimum speed/power

• TTL-compatible inputs and outputs

• When the write operation is active (CE and WE LOW)

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. Data on the four IO pins (IO₀

through IO₃) is then written into the location specified on the

address pins (A₀through A₁₇).

• CY7C106DavailableinPb-free28-pin400-MilwideMolded

SOJ package. CY7C1006D available in Pb-free 28-pin

300-Mil wide Molded SOJ package

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins appears on the four IO pins.

Logic Block Diagram

INPUT BUFFER

256K x 4

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05459 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 22, 2007

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与CY7C106D相关器件

型号	品牌	获取价格	描述	数据表
CY7C106D-10VXC	CYPRESS	获取价格	Standard SRAM, 256KX4, 10ns, CMOS, PDSO28, 0.400 INCH, LEAD FREE, SOJ-28
CY7C106D-10VXI	CYPRESS	获取价格	1-Mbit (256K x 4) Static RAM
CY7C106D-10VXIT	CYPRESS	获取价格	暂无描述
CY7C106D-12VXC	CYPRESS	获取价格	Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.400 INCH, LEAD FREE, SOJ-28
CY7C106D-12VXI	CYPRESS	获取价格	Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.400 INCH, LEAD FREE, SOJ-28
CY7C106L-20VC	CYPRESS	获取价格	Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C106L-25VC	CYPRESS	获取价格	Standard SRAM, 256KX4, 25ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C106L-35VC	CYPRESS	获取价格	Standard SRAM, 256KX4, 35ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C107	CYPRESS	获取价格	1M x 1 Static RAM
CY7C107-12VC	CYPRESS	获取价格	1M x 1 Static RAM

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