CY7C1071DV33
32-Mbit (2 M × 16) Static RAM
32-Mbit (2
M × 16) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 12 ns
The CY7C1071DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 16 bits. The input and output
pins (I/O0 through I/O15) are placed in a high impedance state
when:
■ Low active power
❐ ICC = 250 mA at 12 ns
■ Deselected (CE HIGH)
■ Low Complementary Metal Oxide Semiconductor (CMOS)
standby power
■ Outputs are disabled (OE HIGH)
❐ ISB2 = 50 mA
■ Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ The write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A20). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A20).
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Available in Pb-free 48-ball FBGA package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
2M × 16
IO0–IO7
A(10:0)
RAM ARRAY
IO8–IO15
COLUMN DECODER
A(20:11)
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-12063 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 28, 2011
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