CY7C1079DV33
32-Mbit (4 M × 8) Static RAM
32-Mbit (4
M × 8) Static RAM
Features
Functional Description
■ High Speed
❐ tAA = 12 ns
The CY7C1079DV33 is a high performance CMOS Static RAM
organized as 4,194,304 words by 8 bits.
To write to the device, take Chip Enable (CE[1]) and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A21).
To read from the device, take Chip Enable (CE [1]) LOW and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
See Truth Table (Single Chip Enable) on page 9 for a complete
description of Read and Write modes.
■ Low Active Power
❐ ICC = 250 mA at 12 ns
■ Low CMOS Standby Power
❐ ISB2 = 50 mA
■ Operating Voltages of 3.3 ± 0.3 V
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ TTL Compatible Inputs and Outputs
■ Available in Pb-free 48-ball FBGA Package
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE [1] HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE [1] LOW and WE LOW).
The CY7C1079DV33 is available in a 48-ball FBGA package.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
IO0 – IO7
4M x 8
A4
ARRAY
A5
A6
A7
A8
A9
WE
OE
COLUMN
DECODER
[1]
CE
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and
1
CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
2
1
2
Cypress Semiconductor Corporation
Document Number: 001-50282 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 27, 2011
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