5秒后页面跳转
CY7C1079DV33 PDF预览

CY7C1079DV33

更新时间: 2024-12-01 09:43:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 463K
描述
32-Mbit (4 M x 8) Static RAM TTL Compatible Inputs and Outputs

CY7C1079DV33 数据手册

 浏览型号CY7C1079DV33的Datasheet PDF文件第2页浏览型号CY7C1079DV33的Datasheet PDF文件第3页浏览型号CY7C1079DV33的Datasheet PDF文件第4页浏览型号CY7C1079DV33的Datasheet PDF文件第5页浏览型号CY7C1079DV33的Datasheet PDF文件第6页浏览型号CY7C1079DV33的Datasheet PDF文件第7页 
CY7C1079DV33  
32-Mbit (4 M × 8) Static RAM  
32-Mbit (4  
M × 8) Static RAM  
Features  
Functional Description  
High Speed  
tAA = 12 ns  
The CY7C1079DV33 is a high performance CMOS Static RAM  
organized as 4,194,304 words by 8 bits.  
To write to the device, take Chip Enable (CE[1]) and Write Enable  
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A21).  
To read from the device, take Chip Enable (CE [1]) LOW and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
See Truth Table (Single Chip Enable) on page 9 for a complete  
description of Read and Write modes.  
Low Active Power  
ICC = 250 mA at 12 ns  
Low CMOS Standby Power  
ISB2 = 50 mA  
Operating Voltages of 3.3 ± 0.3 V  
2.0 V Data Retention  
Automatic Power Down when Deselected  
TTL Compatible Inputs and Outputs  
Available in Pb-free 48-ball FBGA Package  
The input and output pins (I/O0 through I/O7) are placed in a high  
impedance state when the device is deselected (CE [1] HIGH),  
the outputs are disabled (OE HIGH), or during a write operation  
(CE [1] LOW and WE LOW).  
The CY7C1079DV33 is available in a 48-ball FBGA package.  
Logic Block Diagram  
INPUT BUFFER  
A0  
A1  
A2  
A3  
IO0 – IO7  
4M x 8  
A4  
ARRAY  
A5  
A6  
A7  
A8  
A9  
WE  
OE  
COLUMN  
DECODER  
[1]  
CE  
Note  
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and  
1
CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.  
2
1
2
Cypress Semiconductor Corporation  
Document Number: 001-50282 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 27, 2011  
[+] Feedback  

与CY7C1079DV33相关器件

型号 品牌 获取价格 描述 数据表
CY7C1079DV33-12B2XI CYPRESS

获取价格

32-Mbit (4 M x 8) Static RAM TTL Compatible Inputs and Outputs
CY7C1079DV33-12BAXI CYPRESS

获取价格

32-Mbit (4 M x 8) Static RAM TTL Compatible Inputs and Outputs
CY7C1079DV33-12BAXI INFINEON

获取价格

Asynchronous SRAM
CY7C1079DV33-12BAXIT INFINEON

获取价格

Asynchronous SRAM
CY7C107A-12PC ETC

获取价格

x1 SRAM
CY7C107A-12VC ETC

获取价格

x1 SRAM
CY7C107A-12VCR CYPRESS

获取价格

Standard SRAM, 1MX1, 12ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C107A-12VCT CYPRESS

获取价格

Standard SRAM, 1MX1, 12ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C107A-15DMB ETC

获取价格

x1 SRAM
CY7C107A-15PC ETC

获取价格

x1 SRAM