CY7C1072AV33-10BBI

更新时间： 2024-12-01 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	147K
描述
32-Mbit (1M x 32) Static RAM

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中文翻译

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数据手册

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PRELIMINARY

CY7C1072AV33

32-Mbit (1M x 32) Static RAM

specified on the address pins (A₀through A₁₉). If Byte Enable

B (B_B) is LOW, then data from I/O pins (I/O₈through I/O₁₅) is

written into the location specified on the address pins (A₀

through A₁₉). Likewise, B_Cand B_Dcorrespond with the I/O

pins I/O₁₆to I/O₂₃and I/O₂₄to I/O₃₁, respectively.

Features

• High density 32-Mbit SRAM

• High speed

— t_AA= 10 ns

Reading from the device is accomplished by enabling the chip

by taking CE₁LOW and CE₂HIGH while forcing the Output

Enable (OE) LOW and the Write Enable (WE) HIGH. If the first

Byte Enable (B_A) is LOW, then data from the memory location

specified by the address pins will appear on I/O₀to I/O₇. If Byte

Enable B (B_B) is LOW, then data from memory will appear on

I/O₈to I/O₁₅. Similarly, B_cand B_Dcorrespond to the third and

fourth bytes. See the truth table at the back of this data sheet

for a complete description of read and write modes.

• Low active power

— I_CC= 450 mA

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

• Automatic power-down when deselected

• TTL compatible inputs and outputs

• Available in standard 119-ball FBGA

The input/output pins (I/O₀through I/O₃₁) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH/CE₂LOW), the outputs are disabled (OE HIGH), the

byte selects are disabled (B_A-DHIGH), or during a Write

operation (CE₁LOW, CE₂HIGH, and WE LOW).

Functional Description

The CYM1072AV33 is a 3.3V high-performance 32-Megabit

static RAM organized as 1M words by 32 bits.

The CY7C1072AV33 is available in a 119-ball grid array

(FBGA) package.

Writing to the device is accomplished by enabling the chip

(CE₁LOW and CE₂HIGH) while forcing the Write Enable

(WE) input LOW. If Byte Enable A (B_A) is LOW, then data from

the I/O pins (I/O₀through I/O₇), is written into the location

CE₁

CE₂

Logic Block Diagram

INPUT BUFFERS

B_A

B_B

A₀

A₁

A₂

A₃

A₄

B_C

B_D

1024K x 32

ARRAY

I/O₀–I/O₃₁

A₅

A₆

A₇

A₈

A₉

COLUMN

DECODER

Selection Guide

CY7C1072AV33-10

CY7C1072AV33-12

Unit

Maximum Access Time

Maximum Operating Current

Maximum Standby Current

450

100

400

100

Cypress Semiconductor Corporation

Document #: 38-05635 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 1, 2005

12 3 4 5 6 7...9

中文翻译

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与CY7C1072AV33-10BBI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1072AV33-12BBC	CYPRESS	获取价格	32-Mbit (1M x 32) Static RAM
CY7C1072AV33-12BBI	CYPRESS	获取价格	32-Mbit (1M x 32) Static RAM
CY7C107-35DC	ETC	获取价格	x1 SRAM
CY7C107-35DMB	ETC	获取价格	x1 SRAM
CY7C107-35LC	ETC	获取价格	x1 SRAM
CY7C107-35LMB	ETC	获取价格	x1 SRAM
CY7C107-35PC	ETC	获取价格	x1 SRAM
CY7C107-35VC	ETC	获取价格	x1 SRAM
CY7C107-35VCT	CYPRESS	获取价格	Standard SRAM, 1MX1, 35ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C107-45DC	ETC	获取价格	x1 SRAM

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