Datasheet > CY7C1071AV33

CY7C1071AV33

更新时间： 2024-12-01 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	148K
描述
32-Mbit (2M x 16) Static RAM

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中文翻译

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数据手册

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CY7C1071AV33 数据手册

PRELIMINARY

CY7C1071AV33

32-Mbit (2M x 16) Static RAM

Low Enable (BLE) is LOW, then data from the I/O pins (I/O₀

through I/O₇), is written into the location specified on the ad-

dress pins (A₀through A₂₀). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₂₀).

Features

• High density 32-Mbit SRAM

• High speed

— t_AA= 10 ns

Reading from the device is accomplished by enabling the chip

by taking CE HIGH while forcing the Output Enable (OE) LOW

and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on I/O₀to I/O₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O₈to

I/O₁₅. See the truth table at the back of this data sheet for a

complete description of Read and Write modes.

• Low active power

— I_CC= 450 mA

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Available in standard 119-ball FBGA

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE

LOW), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE HIGH, and WE LOW).

Functional Description

The CY7C1071AV33 is a 3.3V high-performance 32-Megabit

static RAM organized as a 2,097,152 words by 16 bits.

The CY7C1071AV33 is available in a 119-ball grid array

(FBGA) package.

Writing to the device is accomplished by enabling the chip (CE

HIGH) while forcing the Write Enable (WE) input LOW. If Byte

Logic Block Diagram

DATA-IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

2048K × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

BLE

Power-down

Circuit

Cypress Semiconductor Corporation

Document #: 38-05634 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 1, 2005

12 3 4 5 6 7...10

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