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CY7C106BN_11 PDF预览

CY7C106BN_11

更新时间: 2024-11-30 09:43:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 396K
描述
256K x 4 Static RAM

CY7C106BN_11 数据手册

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CY7C106BN  
256K x 4 Static RAM  
Features  
Functional Description  
The CY7C106BN is a high performance CMOS static RAMs  
organized as 262,144 words by 4 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), an active LOW  
Output Enable (OE), and tristate drivers. These devices have an  
automatic power down feature that reduces power consumption  
by more than 65% when the devices are deselected.  
High speed  
tAA = 15 ns  
CMOS for optimum speed/power  
Low active power  
495 mW  
Writing to the devices is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O  
pins (I/O0 through I/O3) is then written into the location specified  
on the address pins (A0 through A17).  
Low standby power  
275 mW  
2.0V data retention (optional)  
Reading from the devices is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins will appear on the four I/O  
pins.  
Automatic power down when deselected  
TTL-compatible inputs and outputs  
The four input/output pins (I/O0 through I/O3) are placed in a high  
impedance state when the devices are deselected (CE HIGH),  
the outputs are disabled (OE HIGH), or during a write operation  
(CE and WE LOW).  
The CY7C106BN is available in a standard 400-mil-wide SOJ.  
Logic Block Diagram  
INPUTBUFFER  
A
1
A
I/O  
I/O  
I/O  
I/O  
2
3
2
1
0
A
3
A
4
A
5
512 x 512 x 4  
ARRAY  
A
6
A
7
A
8
A
9
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-06429 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 15, 2010  
[+] Feedback  

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