Datasheet > CY7C10612G30-10ZSXIT

CY7C10612G30-10ZSXIT

更新时间： 2024-09-17 01:03:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	455K
描述
16-Mbit (1M Ã 16) Static RAM

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CY7C10612G

CY7C10612GE

16-Mbit (1M × 16) Static RAM

16-Mbit (1M

× 16) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C10612G and CY7C10612GE are high performance

CMOS fast static RAM devices with embedded ECC. These

devices are offered in single chip enable option. The

CY7C10612GE device includes an error indication pin that

signals an error-detection and correction event during a read

cycle.

■ Embedded error-correcting code (ECC) for single-bit error

correction

■ Low active power

❐ I_CC= 90 mA typical

To write to the device, take Chip Enables (CE) and Write Enable

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇), is written into the location

specified on the address pins (A₀through A₁₉). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₉).

■ Low CMOS standby power

❐ I_SB2= 20 mA typical

■ Operating voltages of 3.3 ± 0.3 V

■ 1.0 V data retention

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See Truth Table on page 14 for a

complete description of Read and Write modes.

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ ERR pin to indicate 1-bit error detection and correction

■ Available in Pb-free 54-pin TSOP II package

The input or output pins (I/O₀through I/O₁₅) are placed in a high

impedance state when the device is deselected (CE HIGH), the

outputs are disabled (OE HIGH), the BHE and BLE are disabled

(BHE, BLE HIGH), or during a write operation (CE LOW and WE

LOW).

On the CY7C10612GE devices the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = high). See the Truth Table

on page 14 for a complete description of read and write modes.

The CY7C10612G and CY7C10612GE are available in a 54-pin

TSOP II package.

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Access Time

-10

Unit

Maximum Operating Current

110

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document Number: 001-88702 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 3, 2018

12 3 4 5 6 7...19

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与CY7C10612G30-10ZSXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C10612GE	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612GE30-10ZSXI	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612GE30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C10612GE30-10ZSXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612GE30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C10612GN	CYPRESS	获取价格	16-Mbit (1M words Ã 16 bit) Static RAM
CY7C10612GN30-10ZSXI	CYPRESS	获取价格	16-Mbit (1M words Ã 16 bit) Static RAM
CY7C10612GN30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C10612GN30-10ZSXIT	CYPRESS	获取价格	16-Mbit (1M words Ã 16 bit) Static RAM
CY7C10612GN30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM

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