5秒后页面跳转
捷配首页

Datasheet > CY7C1061AV33
CY7C1061AV33 PDF预览

CY7C1061AV33

更新时间： 2024-11-04 22:03:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 273K
描述
1M x 16 Static RAM

阅读下载

中文翻译

获取价格

CY7C1061AV33 数据手册

 浏览型号CY7C1061AV33的Datasheet PDF文件第2页浏览型号CY7C1061AV33的Datasheet PDF文件第3页浏览型号CY7C1061AV33的Datasheet PDF文件第4页浏览型号CY7C1061AV33的Datasheet PDF文件第5页浏览型号CY7C1061AV33的Datasheet PDF文件第6页浏览型号CY7C1061AV33的Datasheet PDF文件第7页 
CY7C1061AV33  
1M x 16 Static RAM  
specified on the address pins (A0 through A19). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A19).  
Features  
• High speed  
— tAA = 8, 10, 12 ns  
Reading from the device is accomplished by enabling the chip  
by taking CE1 LOW and CE2 HIGH while forcing the Output  
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte  
Low Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table at the back of this data  
sheet for a complete description of Read and Write modes.  
• Low active power  
— 1080 mW (max.)  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1 and CE2 features  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the  
BHE and BLE are disabled (BHE, BLE HIGH), or during a  
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
Functional Description  
The CY7C1061AV33 is a high-performance CMOS Static  
RAM organized as 1,048,576 words by 16 bits.  
Writing to the device is accomplished by enabling the chip  
(CE1 LOW and CE2 HIGH) while forcing the Write Enable  
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
The CY7C1061AV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-ball fine-pitch ball grid array (FBGA) package.  
Pin Configuration  
Logic Block Diagram  
TSOP II (Top View)  
1
54 I/O  
11  
INPUT BUFFER  
I/O  
V
12  
CC  
53  
52  
51  
50  
V
I/O  
I/O  
2
3
4
5
6
SS  
I/O  
13  
14  
10  
A
0
A
1
I/O  
V
9
V
CC  
SS  
A
2
I/O  
49 I/O  
15  
8
A
3
4
I/O –I/O  
1M x 16  
ARRAY  
0
7
A
A
3
A
A
1
A
48  
47  
A
5
A
6
7
A
4
8
A
5
6
4096 x 4096  
I/O –I/O  
8
15  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
A
7
A
9
2
A
10  
11  
12  
13  
A
8
7
A
A
9
8
A
0
NC  
9
BHE  
CE  
OE  
1
V
V
CC  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
SS  
WE  
DNU (Do Not Use)  
BLE  
COLUMN  
DECODER  
CE  
2
A
19  
A
10  
A
18  
A
11  
A
12  
A
13  
A
A
A
17  
16  
15  
BHE  
WE  
A
14  
I/O  
V
I/O  
V
0
7
CE  
2
1
CC  
SS  
CE  
24  
25  
26  
27  
I/O  
I/O  
OE  
BLE  
6
5
1
2
I/O  
I/O  
V
V
SS  
CC  
I/O  
I/O  
3
4
Selection Guide  
-8  
8
-10  
10  
-12  
12  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Commercial  
Industrial  
300  
300  
50  
275  
275  
50  
260  
260  
50  
mA  
Maximum CMOS Standby Current  
Commercial/Industrial  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05256 Rev. *D  
Revised February 21, 2003  
1234567...11

中文翻译

下载PDF

与CY7C1061AV33相关器件

型号 品牌 获取价格 描述 数据表
CY7C1061AV33_07 CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061AV33_11 CYPRESS

获取价格

 		16-Mbit (1 M × 16) Static RAM
CY7C1061AV33_12 CYPRESS

获取价格

 		16-Mbit (1 M × 16) Static RAM
CY7C1061AV33-10BAC CYPRESS

获取价格

 		1M x 16 Static RAM
CY7C1061AV33-10BAI CYPRESS

获取价格

 		1M x 16 Static RAM
CY7C1061AV33-10BAXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061AV33-10BAXIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA60, 8 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-60
CY7C1061AV33-10ZC CYPRESS

获取价格

 		1M x 16 Static RAM
CY7C1061AV33-10ZCT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061AV33-10ZI CYPRESS

获取价格

 		1M x 16 Static RAM

与CY7C1061AV33相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证