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CY7C1061AV33-10ZXI PDF预览

CY7C1061AV33-10ZXI

更新时间： 2024-11-19 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 642K
描述
16-Mbit (1M x 16) Static RAM

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CY7C1061AV33-10ZXI 数据手册

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CY7C1061AV33  
16-Mbit (1M x 16) Static RAM  
Features  
Functional Description  
• High speed  
The CY7C1061AV33 is a high performance CMOS Static RAM  
organized as 1,048,576 words by 16 bits.  
— tAA = 10 ns  
To write to the device, enable the chip (CE1 LOW and CE2  
HIGH) while forcing the Write Enable (WE) input LOW. If Byte  
Low Enable (BLE) is LOW, then data from IO pins (IO0 through  
IO7), is written into the location specified on the address pins  
(A0 through A19). If Byte High Enable (BHE) is LOW, then data  
from IO pins (IO8 through IO15) is written into the location  
specified on the address pins (A0 through A19).  
• Low active power  
— 990 mW (max)  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
• Automatic power down when deselected  
• TTL compatible inputs and outputs  
• Easy memory expansion with CE1 and CE2 features  
To read from the device, enable the chip by taking CE1 LOW  
and CE2 HIGH while forcing the Output Enable (OE) LOW and  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on IO0 to IO7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on IO8 to  
IO15. See “Truth Table” on page 7 for a complete description  
of Read and Write modes.  
• Available in Pb-free and non Pb-free 54-pin TSOP II  
package and non Pb-free 60-ball fine pitch ball grid array  
(FBGA) package  
The input/output pins (IO0 through IO15) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the  
BHE and BLE are disabled (BHE, BLE HIGH), or a Write  
operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW).  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
A
4
3
IO0–IO7  
1M x 16  
ARRAY  
A
A
5
IO8–IO15  
A
6
A
7
A
8
9
A
COLUMN  
DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05256 Rev. *G  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 26, 2007  
[+] Feedback  
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CY7C1061AV33-10ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1061DV33-10ZSXI CYPRESS

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