Datasheet > CY7C1061AV33_11

CY7C1061AV33_11

更新时间： 2024-11-05 09:43:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	417K
描述
16-Mbit (1 M × 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1061AV33_11 数据手册

CY7C1061AV33

16-Mbit (1 M × 16) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C1061AV33 is a high performance CMOS Static RAM

organized as 1,048,576 words by 16 bits.

■ Low active power

❐ 990 mW (max)

To write to the device, enable the chip (CE₁LOW and CE₂HIGH)

while forcing the Write Enable (WE) input LOW. If Byte Low

Enable (BLE) is LOW, then data from I/O pins (I/O₀through I/O₇),

is written into the location specified on the address pins (A₀

through A₁₉). If Byte High Enable (BHE) is LOW, then data from

I/O pins (I/O₈through I/O₁₅) is written into the location specified

on the address pins (A₀through A₁₉).

■ Operating voltages of 3.3 ± 0.3 V

■ 2.0 V data retention

■ Automatic power down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE₁and CE₂features

To read from the device, enable the chip by taking CE₁LOW and

CE₂HIGH while forcing the Output Enable (OE) LOW and the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins will

appear on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then

data from memory will appear on I/O₈to I/O₁₅. See “Truth Table”

on page 8 for a complete description of Read and Write modes.

■ Available in Pb-free and non Pb-free 54-pin TSOP II package

and non Pb-free 60-ball fine pitch ball grid array (FBGA)

package

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH/CE₂LOW), the outputs are disabled (OE HIGH), the BHE

and BLE are disabled (BHE, BLE HIGH), or a Write operation is

in progress (CE₁LOW, CE₂HIGH, and WE LOW).

Logic Block Diagram

INPUT BUFFER

I/O₀–I/O₇

1M x 16

ARRAY

I/O₈–I/O₁₅

COLUMN

DECODER

BHE

CE₂

CE₁

BLE

Cypress Semiconductor Corporation

Document #: 38-05256 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 2, 2011

[+] Feedback

12 3 4 5 6 7...13

中文翻译

下载PDF

与CY7C1061AV33_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1061AV33_12	CYPRESS	获取价格	16-Mbit (1 M Ã 16) Static RAM
CY7C1061AV33-10BAC	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10BAI	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10BAXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY7C1061AV33-10BAXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PBGA60, 8 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-60
CY7C1061AV33-10ZC	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10ZCT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061AV33-10ZI	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10ZIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061AV33-10ZXC	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM

与CY7C1061AV33_11相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

10
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1061AV33_11

CY7C1061AV33_11 数据手册

与CY7C1061AV33_11相关器件

与CY7C1061AV33_11相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1061AV33_11

CY7C1061AV33_11 数据手册

与CY7C1061AV33_11相关器件

与CY7C1061AV33_11相关文章

您还可以找

您在本页遇到什么问题？