Datasheet > CY7C1061AV33_07

CY7C1061AV33_07

更新时间： 2024-09-16 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	642K
描述
16-Mbit (1M x 16) Static RAM

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CY7C1061AV33_07 数据手册

CY7C1061AV33

16-Mbit (1M x 16) Static RAM

Features

Functional Description

• High speed

The CY7C1061AV33 is a high performance CMOS Static RAM

organized as 1,048,576 words by 16 bits.

— t_AA= 10 ns

To write to the device, enable the chip (CE₁LOW and CE₂

HIGH) while forcing the Write Enable (WE) input LOW. If Byte

Low Enable (BLE) is LOW, then data from IO pins (IO₀through

IO₇), is written into the location specified on the address pins

(A₀through A₁₉). If Byte High Enable (BHE) is LOW, then data

from IO pins (IO₈through IO₁₅) is written into the location

specified on the address pins (A₀through A₁₉).

• Low active power

— 990 mW (max)

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

• Automatic power down when deselected

• TTL compatible inputs and outputs

• Easy memory expansion with CE₁and CE₂features

To read from the device, enable the chip by taking CE₁LOW

and CE₂HIGH while forcing the Output Enable (OE) LOW and

the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on IO₀to IO₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on IO₈to

IO₁₅. See “Truth Table” on page 7 for a complete description

of Read and Write modes.

• Available in Pb-free and non Pb-free 54-pin TSOP II

package and non Pb-free 60-ball fine pitch ball grid array

(FBGA) package

The input/output pins (IO₀through IO₁₅) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH/CE₂LOW), the outputs are disabled (OE HIGH), the

BHE and BLE are disabled (BHE, BLE HIGH), or a Write

operation is in progress (CE₁LOW, CE₂HIGH, and WE LOW).

Logic Block Diagram

INPUT BUFFER

IO₀–IO₇

1M x 16

ARRAY

IO₈–IO₁₅

COLUMN

DECODER

BHE

CE₂

CE₁

BLE

Cypress Semiconductor Corporation

Document #: 38-05256 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 26, 2007

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与CY7C1061AV33_07相关器件

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CY7C1061AV33_11	CYPRESS	获取价格	16-Mbit (1 M × 16) Static RAM
CY7C1061AV33_12	CYPRESS	获取价格	16-Mbit (1 M Ã 16) Static RAM
CY7C1061AV33-10BAC	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10BAI	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10BAXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY7C1061AV33-10BAXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PBGA60, 8 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-60
CY7C1061AV33-10ZC	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10ZCT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061AV33-10ZI	CYPRESS	获取价格	1M x 16 Static RAM
CY7C1061AV33-10ZIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54