Datasheet > CY7C1049L-25VI

CY7C1049L-25VI

更新时间： 2024-11-04 21:58:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	131K
描述
512K x 8 Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1049L-25VI 数据手册

049

PRELIMINARY

CY7C1049

512K x 8 Static RAM

is provided by an active LOW chip enable (CE), an active LOW

output enable (OE), and three-state drivers. Writing to the de-

vice is accomplished by taking chip enable (CE) and write en-

able (WE) inputs LOW. Data on the eight I/O pins (I/O₀through

I/O₇) is then written into the location specified on the address

pins (A₀through A₁₈).

Features

• High speed

— t_AA= 15 ns

• Low active power

— 1210 mW (max.)

Reading from the device is accomplished by taking chip en-

able (CE) and output enable (OE) LOW while forcing write en-

able (WE) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear on

the I/O pins.

• Low CMOS standby power (Commercial L version)

— 2.75 mW (max.)

• 2.0V Data Retention (400 µW at 2.0V retention)

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Functional Description

The CY7C1049 is available in a standard 400-mil-wide 36-pin

SOJ package with center power and ground (revolutionary)

pinout.

The CY7C1049 is a high-performance CMOS static RAM or-

ganized as 524,288 words by 8 bits. Easy memory expansion

Logic Block Diagram

Pin Configuration

SOJ

Top View

A₀

A₁

A₁₈

A₁₇

A₁₆

A₁₅

A₂

A₃

A₄

I/O₀

I/O₁

V_CC

I/O₇

I/O₆

I/O

GND

V_CC

I/O₅

I/O₄

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

INPUT BUFFER

GND 10

I/O

I/O₂

I/O3

A₅

A₆

A₇

A₈

A₉

I/O

512K x 8

ARRAY

1049–2

I/O

POWER

DOWN

COLUMN

DECODER

I/O

1049–1

Selection Guide

7C1049-12

7C1049-15

7C1049-17

7C1049-20

7C1049-25

Maximum Access Time (ns)

240

220

195

185

180

Maximum Operating Current (mA)

Maximum CMOS Standby

Current (mA)

Com’l

Ind’l

0.5

Military

Shaded areas contain advance information.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05063 Rev. **

Revised August 31, 2001

12 3 4 5 6 7...10

中文翻译

下载PDF

与CY7C1049L-25VI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1049L-25VM	CYPRESS	获取价格	512K x 8 Static RAM
CY7C1049L-35VC	CYPRESS	获取价格	Standard SRAM, 512KX8, 35ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33-12VC	CYPRESS	获取价格	Standard SRAM, 512KX8, 12ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33-15VC	CYPRESS	获取价格	Standard SRAM, 512KX8, 15ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33-17VC	CYPRESS	获取价格	Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33-17VCT	CYPRESS	获取价格	Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33-20VI	CYPRESS	获取价格	Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
CY7C1049V33L-12VC	ETC	获取价格	x8 SRAM
CY7C1049V33L-15VC	ETC	获取价格	x8 SRAM
CY7C1049V33L-17VC	CYPRESS	获取价格	Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36

与CY7C1049L-25VI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1049L-25VI

CY7C1049L-25VI 数据手册

与CY7C1049L-25VI相关器件

与CY7C1049L-25VI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1049L-25VI

CY7C1049L-25VI 数据手册

与CY7C1049L-25VI相关器件

与CY7C1049L-25VI相关文章

您还可以找

您在本页遇到什么问题？