Datasheet > CY7C1059DV33_07

CY7C1059DV33_07

更新时间： 2024-09-16 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	315K
描述
8-Mbit (1M x 8) Static RAM

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数据手册

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CY7C1059DV33_07 数据手册

CY7C1059DV33

8-Mbit (1M x 8) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C1059DV33^[1]is a high performance CMOS Static RAM

organized as 1M words by 8 bits. Easy memory expansion is

provided by an active LOW Chip Enable (CE), an active LOW

Output Enable (OE), and tri-state drivers. To write to the device,

take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data

on the eight IO pins (IO₀through IO₇) is then written into the

location specified on the address pins (A₀through A₁₉).

■ Low active power

❐ I_CC= 110 mA at 10 ns

■ Low CMOS standby power

❐ I_SB2= 20 mA

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the IO pins.

■ 2.0V data retention

■ Automatic power down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 44-pin TSOP II package

The eight input or output pins (IO₀through IO₇) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE LOW, and WE LOW).

The CY7C1059DV33 is available in 36-ball FBGA and 44-pin

TSOP II packages with center power and ground (revolutionary)

pinout.

Logic Block Diagram

INPUT BUFFER

1M x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For guidelines about SRAM system design, refer to the Cypress application note AN1064, SRAM System Guidelines available at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-00061 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 26, 2007

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