Datasheet > CY7C10612DV33

CY7C10612DV33

更新时间： 2024-09-16 06:51:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	414K
描述
16-Mbit (1M x 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C10612DV33 数据手册

CY7C10612DV33

16-Mbit (1M x 16) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C10612DV33 is a high performance CMOS Static RAM

organized as 1,048,576 words by 16 bits.

To write to the device, take Chip Enables (CE) and Write Enable

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇), is written into the location

specified on the address pins (A₀through A₁₉). If Byte High

■ Low active power

❐ I_CC= 175 mA at 10 ns

■ Low CMOS standby power

❐ I_SB2= 25 mA

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

)

is written into the location specified on the address pins (A₀

through A₁₉).

■ Operating voltages of 3.3 ± 0.3V

■ 2.0V data retention

To read from the device, take Chip Enables (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the Truth Table on page 9 for a

complete description of Read and Write modes.

■ Automatic power down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 54-Pin TSOP II package

The input or output pins (IO₀through IO₁₅) are placed in a high

impedance state when the device is deselected (CE HIGH), the

outputs are disabled (OE HIGH), the BHE and BLE are disabled

(BHE, BLE HIGH), or during a write operation (CE LOW and WE

LOW).

The CY7C10612DV33 is available in a 54-Pin TSOP II package

with center power and ground (revolutionary) pinout.

Logic Block Diagram

INPUT BUFFER

IO₀– IO₇

1M x 16

ARRAY

IO₈– IO₁₅

COLUMN

DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-49315 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2009

[+] Feedback

12 3 4 5 6 7...10

中文翻译

下载PDF

与CY7C10612DV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C10612DV33_11	CYPRESS	获取价格	16-Mbit (1 M × 16) Static RAM
CY7C10612DV33-10ZSXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY7C10612G	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXI	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C10612G30-10ZSXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C10612GE	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612GE30-10ZSXI	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612GE30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM