Datasheet > CY7C1059H30-10ZSXI

CY7C1059H30-10ZSXI

更新时间： 2024-11-06 14:56:39

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
25页	374K
描述
Asynchronous SRAM

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CY7C1059H/CY7C1059HE

8-Mbit (1M words × 8 bit) static RAM with

error-correcting code (ECC)

Features

• High speed

- t_AA= 10 ns

• Embedded error-correcting code (ECC) for single-bit error correction

• Low active and standby currents

- I_CC= 90 mA typical at 100 MHz

- I_SB2= 20 mA typical

• Operating voltage range: 2.2 V to 3.6 V

• 1.0-V data retention

• Transistor-transistor logic (TTL) compatible inputs and outputs

• ERR pin to indicate 1-bit error detection and correction

• Available in Pb-free 44-pin TSOP II package

Functional description

The CY7C1059H and CY7C1059HE are dual chip enable high-performance CMOS fast static RAM devices with

embedded ECC. The CY7C1059H device is available in standard pin configurations. The CY7C1059HE device

includes a single bit error indication pin (ERR) that signals the host processor in the case of an ECC error-detection

and correction event.

To write to the device, take chip enables (CE₁LOW and CE₂HIGH) and write enable (WE) input LOW. Data on the

eight I/O pins (I/O₀through I/O₇) is then written into the location specified on the address pins (A₀through A₂₀).

To read from the device, take chip enables (CE₁LOW and CE₂HIGH) and output enable (OE) LOW while forcing

the write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the

address pins will appear on the I/O pins. See Truth table – CY7C1059H/CY7C1059HE on page 18 for a complete

description of read and write modes. The input and output pins (I/O₀through I/O₇) are placed in a high

impedance state when the device is deselected (CE₁HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW, CE₂HIGH, and WE LOW).

On CY7C1059HE devices, the detection and correction of a single-bit error in the accessed location is indicated

by the assertion of the ERR output (ERR = High) ^[1]

All I/Os (I/O₀through I/O₇) are placed in a high impedance state when the device is deselected (CE₁HIGH or CE₂

LOW), and control signals are de-asserted (CE₁/ CE₂, OE, WE). CY7C1059H and CY7C1059HE devices are available

in a 44-pin TSOP II package with center power and ground (revolutionary) pinout package.

Note

1. Automatic write back on error detection feature is not supported in this device.

Preliminary datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 25

002-34169 Rev. **

2021-11-02

12 3 4 5 6 7...25

中文翻译

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与CY7C1059H30-10ZSXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1059H30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C10612DV33	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY7C10612DV33_11	CYPRESS	获取价格	16-Mbit (1 M × 16) Static RAM
CY7C10612DV33-10ZSXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY7C10612G	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXI	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C10612G30-10ZSXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM
CY7C10612G30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C10612GE	CYPRESS	获取价格	16-Mbit (1M Ã 16) Static RAM

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