Datasheet > CY7C1051DV33

CY7C1051DV33

更新时间： 2024-11-05 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	571K
描述
8-Mbit (512K x 16) Static RAM

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中文翻译

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数据手册

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CY7C1051DV33 数据手册

PRELIMINARY

CY7C1051DV33

8-Mbit (512K x 16) Static RAM

Features

Functional Description^[1]

• High speed

The CY7C1051DV33 is a high-performance CMOS Static

RAM organized as 512K words by 16 bits.

— t_AA= 10 ns

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,

then data from IO pins (IO₀–IO₇), is written into the location

specified on the address pins (A₀–A₁₈). If Byte HIGH Enable

(BHE) is LOW, then data from IO pins (IO₈–IO₁₅) is written into

the location specified on the address pins (A₀–A₁₈).

• Low active power

— I_CC= 110 mA @ 10 ns

• Low CMOS standby power

— I_SB2= 20 mA

• 2.0V data retention

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte LOW Enable (BLE) is LOW, then data from the memory

location specified by the address pins will appear on IO₀–IO₇.

If Byte HIGH Enable (BHE) is LOW, then data from memory

will appear on IO₈to IO₁₅. See the “Truth Table” on page 8 for

a complete description of Read and Write modes.

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• Available in lead-free 48-ball FBGA and 44-pin TSOP II

packages

The input/output pins (IO₀–IO₁₅

)

are placed in

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,

and WE LOW) is in progress.

The CY7C1051DV33 is available in a 44-pin TSOP II package

with center power and ground (revolutionary) pinout, as well

as a 48-ball fine-pitch ball grid array (FBGA) package.

Logic Block Diagram

INPUT BUFFER

IO₀–IO₇

512K × 16

ARRAY

IO₈–IO₁₅

COLUMN

DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-00063 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 9, 2007

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与CY7C1051DV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1051DV33-10BAXI	CYPRESS	获取价格	8-Mbit (512K x 16) Static RAM
CY7C1051DV33-10BAXIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, MO-207, F
CY7C1051DV33-10ZSXI	CYPRESS	获取价格	8-Mbit (512K x 16) Static RAM
CY7C1051DV33-10ZSXIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1051DV33-12BAXIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 12ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, MO-207, F
CY7C1051DV33-12ZSXIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1051DV33-15ZSXE	CYPRESS	获取价格	Standard SRAM, 512KX16, 15ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1051H	CYPRESS	获取价格	8-Mbit (512K Ã 16) Static RAM
CY7C1051H30-10BV1XE	CYPRESS	获取价格	8-Mbit (512K Ã 16) Static RAM
CY7C1051H30-10BV1XE	INFINEON	获取价格	Asynchronous SRAM

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