Datasheet > CY7C1059DV33

CY7C1059DV33

更新时间： 2024-11-06 03:14:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	469K
描述
8-Mbit (1M x 8) Static RAM

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数据手册

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CY7C1059DV33 数据手册

PRELIMINARY

CY7C1059DV33

8-Mbit (1M x 8) Static RAM

Features

Functional Description^[1]

• High speed

The CY7C1059DV33 is a high-performance CMOS Static

RAM organized as 1M words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and tri-state drivers. Writing

to the device is accomplished by taking Chip Enable (CE) and

Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀

through I/O₇) is then written into the location specified on the

address pins (A₀through A₁₉).

— t_AA= 10 ns

• Low active power

— I_CC= 110 mA

• Low CMOS standby power

— I_SB2= 20 mA

• 2.0V data retention

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• Available in lead-free 36-ball FBGA and 44-pin TSOP II

ZS44 packages

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a Write

operation (CE LOW, and WE LOW).

The CY7C1059DV33 is available in 36-ball FBGA and 44-pin

TSOP II package with center power and ground (revolutionary)

pinout.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

1M x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

Note:

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-00061 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 21, 2006

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