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CY7C1051DV33-10ZSXIT PDF预览

CY7C1051DV33-10ZSXIT

更新时间: 2024-11-06 19:42:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
15页 469K
描述
Standard SRAM, 512KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

CY7C1051DV33-10ZSXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSOP2, TSOP44,.46,32
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:1.38
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e3
长度:18.415 mm内存密度:8388608 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.194 mm
最大待机电流:0.02 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.11 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1051DV33-10ZSXIT 数据手册

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CY7C1051DV33  
8-Mbit (512 K × 16) Static RAM  
8-Mbit (512K  
x 16) Static RAM  
Features  
Functional Description  
Temperature ranges  
–40 °C to 85 °C  
The CY7C1051DV33 is a high performance CMOS Static RAM  
organized as 512 K words by 16-bits.  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data  
from I/O pins (I/O0–I/O7), is written into the location specified on  
the address pins (A0–A18). If Byte HIGH Enable (BHE) is LOW,  
then data from I/O pins (I/O8–I/O15) is written into the location  
specified on the address pins (A0–A18).  
High speed  
tAA = 10 ns  
Low active power  
ICC = 110 mA at f = 100 MHz  
Low CMOS standby power  
ISB2 = 20 mA  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte LOW Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on I/O0–I/O7. If  
Byte HIGH Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the Truth Table on page 10 for a  
complete description of read and write modes.  
2.0-V data retention  
Automatic power-down when deselected  
Transistor-transistor logic (TTL)-compatible inputs and outputs  
Easy memory expansion with CE and OE features  
The input/output pins (I/O0–I/O15  
)
are placed in  
a
Available in Pb-free 48-ball fine ball grid array (FBGA) and  
44-pin thin small outline package (TSOP) II packages  
high-impedance state when the device is deselected (CE HIGH),  
the outputs are disabled (OE HIGH), the BHE and BLE are  
disabled (BHE, BLE HIGH), or a write operation (CE LOW, and  
WE LOW) is in progress.  
The CY7C1051DV33 is available in a 44-pin TSOP II package  
with center power and ground (revolutionary) pinout and a  
48-ball FBGA package.  
For a complete list of related documentation,click here.  
Logic Block Diagram  
INPUT BUFFER  
A
A
A
A
A
0
1
2
I/O0–I/O7  
3
4
512 K × 16  
ARRAY  
A
A
I/O8–I/O15  
5
6
A
A
7
8
COLUMN  
DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-00063 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 16, 2015  

CY7C1051DV33-10ZSXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1051DV33-10ZSXI CYPRESS

完全替代

8-Mbit (512K x 16) Static RAM
IS61WV51216BLL-10TLI-TR ISSI

功能相似

Standard SRAM, 512KX16, 10ns, CMOS, PDSO44, LEAD FREE, PLASTIC, TSOP2-44

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