Datasheet > CY7C1051H30-10BV1XE

CY7C1051H30-10BV1XE

更新时间： 2024-09-17 01:14:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	436K
描述
8-Mbit (512K Ã 16) Static RAM

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CY7C1051H Automotive

8-Mbit (512K × 16) Static RAM

8-Mbit (512K

× 16) Static RAM

Features

Functional Description

■ AEC-Q100 qualified

The CY7C1051H^[1]is a high-performance CMOS fast static RAM

automotive part with embedded ECC.

■ Temperature ranges

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data

from I/O pins (I/O₀–I/O₇), is written into the location specified on

the address pins (A₀–A₁₈). If Byte HIGH Enable (BHE) is LOW,

then data from I/O pins (I/O₈–I/O₁₅) is written into the location

specified on the address pins (A₀–A₁₈).

❐ Automotive-E: –40 °C to +125 °C

■ High speed

❐ t_AA= 10 ns

■ Low active and standby currents

❐ I_CC= 90 mA typical

❐ I_SB2= 20 mA typical

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte LOW Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀–I/O₇. If

Byte HIGH Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 11 for a

complete description of read and write modes.

■ 1.0 V data retention

■ Automatic power-down when deselected

■ Transistor-transistor logic (TTL)-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

The input/output pins (I/O₀–I/O₁₅

)

are placed in

■ Available in Pb-free 48-ball very fine-pitch ball grid array

(VFBGA) package

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or a write operation (CE LOW, and

WE LOW) is in progress.

The CY7C1051H is available in 48-ball VFBGA package.

Logic Block Diagram – CY7C1051H

ECC ENCODER

INPUT BUFFER

I/O₀‐I/O₇

I/O₈‐I/O₁₅

MEMORY

ARRAY

COLUMN DECODER

BHE

BLE

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-87624 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 3, 2018

12 3 4 5 6 7...16

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与CY7C1051H30-10BV1XE相关器件

型号	品牌	获取价格	描述	数据表
CY7C1051H30-10BV1XET	CYPRESS	获取价格	8-Mbit (512K Ã 16) Static RAM
CY7C1051H30-10BV1XET	INFINEON	获取价格	Asynchronous SRAM
CY7C1051H30-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1059DV33	CYPRESS	获取价格	8-Mbit (1M x 8) Static RAM
CY7C1059DV33_07	CYPRESS	获取价格	8-Mbit (1M x 8) Static RAM
CY7C1059DV33_09	CYPRESS	获取价格	8-Mbit (1M x 8) Static RAM
CY7C1059DV33-10BAXI	CYPRESS	获取价格	8-Mbit (1M x 8) Static RAM
CY7C1059DV33-10ZSXI	CYPRESS	获取价格	8-Mbit (1M x 8) Static RAM
CY7C1059DV33-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1059DV33-10ZSXIT	CYPRESS	获取价格	Standard SRAM, 1MX8, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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