Datasheet > CY7C1041CV33AUTO

CY7C1041CV33AUTO

更新时间： 2024-02-04 22:27:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	567K
描述
4-Mbit (256 K × 16) Static RAM TTL-compatible inputs and outputs

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CY7C1041CV33AUTO 数据手册

CY7C1041CV33 Automotive

4-Mbit (256 K × 16) Static RAM

4-Mbit (256

K × 16) Static RAM

Features

Functional Description

■ Temperature ranges

❐ Automotive-A: –40 °C to 85 °C

❐ Automotive-E: –40 °C to 125 °C

The CY7C1041CV33 Automotive is a high performance CMOS

static RAM organized as 262,144 words by 16 bits.

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇), is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₇).

■ Pin and function compatible with CY7C1041BNV33

■ High speed

❐ t_AA= 10 ns (Automotive-A)

❐ t_AA= 12 ns (Automotive-E)

■ Low active power

❐ 432 mW (max)

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. For more information, see the Truth

Table on page 10 for a complete description of Read and Write

modes.

■ 2.0 V data retention

■ Automatic power down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

The input and output pins (I/O₀through I/O₁₅) are placed in a

high impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW

and WE LOW).

■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin

TSOP II and 48-ball FBGA packages

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

256K x 16

RAM Array

I/O –I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-67307 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 11, 2011

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与CY7C1041CV33AUTO相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041D	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041D-10VXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041D-10ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041D-12VXE	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041D-12ZSXE	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041D-15ZSXC	CYPRESS	获取价格	Standard SRAM, 256KX16, 15ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1041DV33	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY7C1041DV33_11	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM

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