Datasheet > CY7C1041DV33_11

CY7C1041DV33_11

更新时间： 2024-12-01 09:43:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	567K
描述
4-Mbit (256 K × 16) Static RAM

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CY7C1041DV33_11 数据手册

CY7C1041DV33

4-Mbit (256 K × 16) Static RAM

4-Mbit (256

K × 16) Static RAM

Features

Functional Description

■ Temperature ranges

The CY7C1041DV33 is a high performance CMOS Static RAM

organized as 256 K words by 16-bits. To write to the device, take

chip enable (CE) and write enable (WE) inputs LOW. If byte low

enable (BLE) is LOW, then data from I/O pins (I/O₀to I/O₇) is

written into the location specified on the address pins (A₀to A₁₇).

If byte high enable (BHE) is LOW, then data from I/O pins (I/O₈

to I/O₁₅) is written into the location specified on the address pins

(A₀to A₁₇).

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A ^[1]: –40 °C to 85 °C

❐ Automotive-E ^[1]: –40 °C to 125 °C

■ Pin and function compatible with CY7C1041CV33

■ High speed

❐ t_AA= 10 ns

To read from the device, take chip enable (CE) and output enable

(OE) LOW while forcing the write enable (WE) HIGH. If BLE is

LOW, then data from the memory location specified by the

address pins appears on I/O₀to I/O₇. If BHE is LOW, then data

from memory appears on I/O₈to I/O₁₅. See the Truth Table on

page 10 for a complete description of read and write modes.

■ Low active power

❐ I_CC= 90 mA at 10 ns (industrial)

■ Low CMOS standby power

❐ I_SB2= 10 mA

■ 2.0 V data retention

The input and output pins (I/O₀to I/O₁₅) are placed in a high

impedance state when the device is deselected (CE HIGH),

outputs are disabled (OE HIGH), BHE and BLE are disabled

(BHE, BLE HIGH), or during a write operation (CE LOW and WE

LOW).

■ Automatic power-down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE and OE features

The CY7C1041DV33 is available in a standard 44-pin 400-mil

wide SOJ and 44-pin TSOP II package with center power and

ground (revolutionary) pinout and a 48-ball fine-pitch ball grid

array (FBGA) package.

■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded

SOJ, and 44-pin TSOP II Packages

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

IO –IO

256K × 16

IO –IO

8 15

COLUMN

DECODER

BHE

BLE

Note

1. Automotive product information is preliminary.

Cypress Semiconductor Corporation

Document Number: 38-05473 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 24, 2011

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与CY7C1041DV33_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041DV33-10BVI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 0.314 X 0.236 INCH, ROHS COMPLIANT, VFBGA-48
CY7C1041DV33-10BVXA	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1041DV33-10VXC	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1041DV33-10VXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10VXIT	CYPRESS	获取价格	暂无描述
CY7C1041DV33-10ZSXA	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM

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