Datasheet > CY7C1041G18-15BVXI

CY7C1041G18-15BVXI

更新时间： 2024-12-02 00:53:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	710K
描述
4-Mbit (256K words Ã 16 bit) Static RAM with Error-Correcting Code (ECC)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1041G18-15BVXI 数据手册

浏览型号CY7C1041G18-15BVXI的Datasheet PDF文件第2页

浏览型号CY7C1041G18-15BVXI的Datasheet PDF文件第3页

浏览型号CY7C1041G18-15BVXI的Datasheet PDF文件第4页

浏览型号CY7C1041G18-15BVXI的Datasheet PDF文件第5页

浏览型号CY7C1041G18-15BVXI的Datasheet PDF文件第6页

CY7C1041G

CY7C1041GE

4-Mbit (256K words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

4-Mbit (256K words

× 16 bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Chip Enable (CE) and

Write Enable (WE) inputs LOW, while providing the data on I/O₀

through I/O₁₅and address on A₀through A₁₇pins. The Byte High

Enable (BHE) and Byte Low Enable (BLE) inputs control write

operations to the upper and lower bytes of the specified memory

location. BHE controls I/O₈through I/O₁₅and BLE controls I/O₀

through I/O₇.

Features

■ High speed

❐ t_AA= 10 ns / 15 ns

■ Embedded ECC for single-bit error correction^[1]

■ Low active and standby currents

❐ Active current: I_CC= 38-mA typical

❐ Standby current: I_SB2= 6-mA typical

Data reads are performed by asserting the Chip Enable (CE) and

Output Enable (OE) inputs LOW and providing the required

■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and

4.5 V to 5.5 V

address on the address lines. Read data is accessible on the I/O

lines (I/O₀through I/O₁₅). Byte accesses can be performed by

asserting the required byte enable signal (BHE or BLE) to read

either the upper byte or the lower byte of data from the specified

address location.

■ 1.0-V data retention

■ TTL-compatible inputs and outputs

All I/Os (I/O₀through I/O₁₅) are placed in a high-impedance state

during the following events:

■ Error indication (ERR) pin to indicate 1-bit error detection and

correction

■ The device is deselected (CE HIGH)

■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA

packages

■ The control signals (OE, BLE, BHE) are de-asserted

On the CY7C1041GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = HIGH)^[1]. See the Truth

Table on page 14 for a complete description of read and write

modes.

Functional Description

CY7C1041G and CY7C1041GE are high-performance CMOS

fast static RAM devices with embedded ECC. Both devices are

offered in single and dual chip-enable options and in multiple pin

configurations. The CY7C1041GE device includes an ERR pin

that signals an error-detection and correction event during a read

cycle.

The logic block diagram is on page 2.

Product Portfolio

Power Dissipation

Speed

Operating I_CC, (mA)

FeaturesandOptions(seePin

V_CCRange

(V)

(ns)

Standby, I_SB2

Product ^[2]

Range

Configurations on page 4)

(mA)

f = f_max

10/15

Typ ^[3]

–

Max

Typ ^[3]

Max

CY7C1041G(E)18 Single or Dual Chip Enables

Industrial 1.65 V–2.2 V

2.2 V–3.6 V

CY7C1041G(E)30

Optional ERR pins

CY7C1041G(E)

4.5 V–5.5 V

Notes

1. This device does not support automatic write-back on error detection.

2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.

3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),

= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.

CC CC CC A

Cypress Semiconductor Corporation

Document Number: 001-91368 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 2, 2016

12 3 4 5 6 7...20

中文翻译

下载PDF

与CY7C1041G18-15BVXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041G18-15BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G18-15VXI	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with
CY7C1041G18-15VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G18-15VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G18-15ZSXI	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with
CY7C1041G18-15ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G18-15ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10BAJXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10BAJXET	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10BVJXI	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with

与CY7C1041G18-15BVXI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1041G18-15BVXI

CY7C1041G18-15BVXI 数据手册

与CY7C1041G18-15BVXI相关器件

与CY7C1041G18-15BVXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1041G18-15BVXI

CY7C1041G18-15BVXI 数据手册

与CY7C1041G18-15BVXI相关器件

与CY7C1041G18-15BVXI相关文章

您还可以找

您在本页遇到什么问题？