Datasheet > CY7C1041G30-10BVJXI

CY7C1041G30-10BVJXI

更新时间： 2024-11-06 00:53:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	710K
描述
4-Mbit (256K words Ã 16 bit) Static RAM with Error-Correcting Code (ECC)

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CY7C1041G

CY7C1041GE

4-Mbit (256K words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

4-Mbit (256K words

× 16 bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Chip Enable (CE) and

Write Enable (WE) inputs LOW, while providing the data on I/O₀

through I/O₁₅and address on A₀through A₁₇pins. The Byte High

Enable (BHE) and Byte Low Enable (BLE) inputs control write

operations to the upper and lower bytes of the specified memory

location. BHE controls I/O₈through I/O₁₅and BLE controls I/O₀

through I/O₇.

Features

■ High speed

❐ t_AA= 10 ns / 15 ns

■ Embedded ECC for single-bit error correction^[1]

■ Low active and standby currents

❐ Active current: I_CC= 38-mA typical

❐ Standby current: I_SB2= 6-mA typical

Data reads are performed by asserting the Chip Enable (CE) and

Output Enable (OE) inputs LOW and providing the required

■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and

4.5 V to 5.5 V

address on the address lines. Read data is accessible on the I/O

lines (I/O₀through I/O₁₅). Byte accesses can be performed by

asserting the required byte enable signal (BHE or BLE) to read

either the upper byte or the lower byte of data from the specified

address location.

■ 1.0-V data retention

■ TTL-compatible inputs and outputs

All I/Os (I/O₀through I/O₁₅) are placed in a high-impedance state

during the following events:

■ Error indication (ERR) pin to indicate 1-bit error detection and

correction

■ The device is deselected (CE HIGH)

■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA

packages

■ The control signals (OE, BLE, BHE) are de-asserted

On the CY7C1041GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = HIGH)^[1]. See the Truth

Table on page 14 for a complete description of read and write

modes.

Functional Description

CY7C1041G and CY7C1041GE are high-performance CMOS

fast static RAM devices with embedded ECC. Both devices are

offered in single and dual chip-enable options and in multiple pin

configurations. The CY7C1041GE device includes an ERR pin

that signals an error-detection and correction event during a read

cycle.

The logic block diagram is on page 2.

Product Portfolio

Power Dissipation

Speed

Operating I_CC, (mA)

FeaturesandOptions(seePin

V_CCRange

(V)

(ns)

Standby, I_SB2

Product ^[2]

Range

Configurations on page 4)

(mA)

f = f_max

10/15

Typ ^[3]

–

Max

Typ ^[3]

Max

CY7C1041G(E)18 Single or Dual Chip Enables

Industrial 1.65 V–2.2 V

2.2 V–3.6 V

CY7C1041G(E)30

Optional ERR pins

CY7C1041G(E)

4.5 V–5.5 V

Notes

1. This device does not support automatic write-back on error detection.

2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.

3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),

= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.

CC CC CC A

Cypress Semiconductor Corporation

Document Number: 001-91368 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 2, 2016

12 3 4 5 6 7...20

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CY7C1041G30-10BVJXI 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1041G30-10BVXI	CYPRESS	完全替代	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, VFBGA-48

与CY7C1041G30-10BVJXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041G30-10BVXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, VFBGA-48
CY7C1041G30-10BVXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10VXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, SOJ-44
CY7C1041G30-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10ZSXE	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, TSOP2-44
CY7C1041G30-10ZSXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1041G30-10ZSXET	INFINEON	获取价格	Asynchronous SRAM

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