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CY7C1041DV33-12BVJXE PDF预览

CY7C1041DV33-12BVJXE

更新时间： 2024-02-03 13:49:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
17页 567K
描述
4-Mbit (256 K × 16) Static RAM

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中文翻译

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CY7C1041DV33-12BVJXE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2, TSOP44,.46,32针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.78
最长访问时间：12 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e4
长度：18.415 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：44字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：256KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.194 mm最大待机电流：0.015 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.095 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：10.16 mmBase Number Matches：1

CY7C1041DV33-12BVJXE 数据手册

 浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第2页浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第3页浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第4页浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第5页浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第6页浏览型号CY7C1041DV33-12BVJXE的Datasheet PDF文件第7页 
CY7C1041DV33  
4-Mbit (256 K × 16) Static RAM  
4-Mbit (256  
K × 16) Static RAM  
Features  
Functional Description  
■ Temperature ranges  
The CY7C1041DV33 is a high performance CMOS Static RAM  
organized as 256 K words by 16-bits. To write to the device, take  
chip enable (CE) and write enable (WE) inputs LOW. If byte low  
enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is  
written into the location specified on the address pins (A0 to A17).  
If byte high enable (BHE) is LOW, then data from I/O pins (I/O8  
to I/O15) is written into the location specified on the address pins  
(A0 to A17).  
❐ Industrial: –40 °C to 85 °C  
❐ Automotive-A [1] : –40 °C to 85 °C  
❐ Automotive-E [1] : –40 °C to 125 °C  
■ Pin and function compatible with CY7C1041CV33  
■ High speed  
❐ tAA = 10 ns  
To read from the device, take chip enable (CE) and output enable  
(OE) LOW while forcing the write enable (WE) HIGH. If BLE is  
LOW, then data from the memory location specified by the  
address pins appears on I/O0 to I/O7. If BHE is LOW, then data  
from memory appears on I/O8 to I/O15. See the Truth Table on  
page 10 for a complete description of read and write modes.  
■ Low active power  
❐ ICC = 90 mA at 10 ns (industrial)  
■ Low CMOS standby power  
❐ ISB2 = 10 mA  
■ 2.0 V data retention  
The input and output pins (I/O0 to I/O15) are placed in a high  
impedance state when the device is deselected (CE HIGH),  
outputs are disabled (OE HIGH), BHE and BLE are disabled  
(BHE, BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
■ Automatic power-down when deselected  
■ TTL compatible inputs and outputs  
■ Easy memory expansion with CE and OE features  
The CY7C1041DV33 is available in a standard 44-pin 400-mil  
wide SOJ and 44-pin TSOP II package with center power and  
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid  
array (FBGA) package.  
■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded  
SOJ, and 44-pin TSOP II Packages  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
IO –IO  
0
7
A
3
4
A
256K × 16  
A
6
IO –IO  
8 15  
5
A
A
7
8
A
COLUMN  
DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
1. Automotive product information is preliminary.  
Cypress Semiconductor Corporation  
Document Number: 38-05473 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 24, 2011  
[+] Feedback  
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CY7C1041DV33-12VXC CYPRESS

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CY7C1041DV33-12VXE CYPRESS

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