5秒后页面跳转
捷配首页

Datasheet > CY7C1041D
CY7C1041D PDF预览

CY7C1041D

更新时间： 2024-12-01 05:19:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 336K
描述
4-Mbit (256K x 16) Static RAM

阅读下载

中文翻译

获取价格

CY7C1041D 数据手册

 浏览型号CY7C1041D的Datasheet PDF文件第2页浏览型号CY7C1041D的Datasheet PDF文件第3页浏览型号CY7C1041D的Datasheet PDF文件第4页浏览型号CY7C1041D的Datasheet PDF文件第5页浏览型号CY7C1041D的Datasheet PDF文件第6页浏览型号CY7C1041D的Datasheet PDF文件第7页 
CY7C1041D  
4-Mbit (256K x 16) Static RAM  
Features  
Functional Description[1]  
• Pin-and function-compatible with CY7C1041B  
• High speed  
— tAA = 10 ns  
The CY7C1041D is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. Writing to the device is  
accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A17).  
• Low active power  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• 2.0 V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
• Availableinlead-free44-Lead(400-Mil)MoldedSOJand  
44-Pin TSOP II packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1041D is available in  
a
standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Pin Configurations  
Logic Block Diagram  
/ TSOPII  
SOJ  
Top View  
INPUT BUFFER  
44  
1
A
A
17  
0
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
A
A
16  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
1
A
0
1
A
A
15  
2
A
A
OE  
3
A
2
3
BHE  
BLE  
A
I/O0–I/O7  
4
A
CE  
A
256K x 16  
4
I/O  
I/O  
0
15  
I/O8–I/O15  
A
5
6
I/O  
I/O  
I/O  
1
14  
13  
12  
A
I/O  
2
A
7
8
I/O  
V
I/O  
A
3
V
SS  
CC  
V
V
SS  
CC  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
9
8
COLUMN  
31  
30  
29  
28  
27  
26  
25  
I/O  
I/O  
I/O  
DECODER  
I/O  
I/O  
WE 17  
NC  
18  
A
A
14  
5
19  
BHE  
A
A
6
13  
WE  
CE  
OE  
A
20  
21  
22  
A
12  
11  
7
A
A
24  
23  
8
A
A
10  
9
BLE  
Note:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Document #: 38-05472 Rev. *C  
Revised March 31, 2006  
[+] Feedback  
1234567...9

中文翻译

下载PDF

与CY7C1041D相关器件

型号 品牌 获取价格 描述 数据表
CY7C1041D-10VXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041D-10ZSXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041D-12VXE CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041D-12ZSXE CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041D-15ZSXC CYPRESS

获取价格

 		Standard SRAM, 256KX16, 15ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1041DV33 CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041DV33_11 CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXIT CYPRESS

获取价格

 		Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 0.314 X 0.236 INCH, ROHS COMPLIANT, VFBGA-48

与CY7C1041D相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证