5秒后页面跳转
捷配首页

Datasheet > CY7C1041D-15ZSXC
CY7C1041D-15ZSXC PDF预览

CY7C1041D-15ZSXC

更新时间： 2024-01-10 10:51:34
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 206K
描述
Standard SRAM, 256KX16, 15ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

阅读下载

中文翻译

获取价格

CY7C1041D-15ZSXC 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2, TSOP44,.46,32针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.6
Is Samacsys：N最长访问时间：15 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e4长度：18.415 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.194 mm最大待机电流：0.01 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.07 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：10.16 mmBase Number Matches：1

CY7C1041D-15ZSXC 数据手册

 浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第2页浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第3页浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第4页浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第5页浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第6页浏览型号CY7C1041D-15ZSXC的Datasheet PDF文件第7页 
CY7C1041D  
PRELIMINARY  
4-Mbit (256K x 16) Static RAM  
is accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A17).  
Features  
• Pin- and function-compatible with CY7C1041B  
• High speed  
— tAA = 10 ns  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
— ICC = 80 mA @ 10 ns (Commercial)  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
• 2.0 V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Available in Lead-Free 44-Lead (400-Mil) Molded SOJ  
V44 and 44-Pin TSOP II ZS44 packages  
The CY7C1041D is available in  
400-mil-wide body width SOJ and 44-pin TSOP II package  
a
standard 44-pin  
Functional Description[1]  
with center power and ground (revolutionary) pinout.  
The CY7C1041D is a high-performance CMOS static RAM  
organized as 262,144 words by 16 bits. Writing to the device  
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
INPUT BUFFER  
A
44  
0
1
A
A
17  
0
A
1
43  
42  
41  
40  
39  
38  
A
A
16  
2
3
4
5
6
1
A
2
A
15  
A
2
I/O0–I/O7  
A
3
A
OE  
BHE  
BLE  
3
A
256K x 16  
4
A
4
I/O8–I/O15  
A
5
CE  
A
6
I/O  
I/O  
7
0
15  
A
7
37  
36  
35  
34  
33  
I/O  
I/O  
8
I/O  
I/O  
1
2
14  
13  
12  
A
8
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
COLUMN  
DECODER  
V
V
CC  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
9
8
I/O  
BHE  
WE 17  
NC  
WE  
CE  
OE  
18  
A
14  
A
5
19  
26  
25  
A
A
6
13  
A
20  
21  
22  
A
7
12  
BLE  
A
11  
A
24  
23  
8
9
A
A
10  
Selection Guide  
7C1041D-10 7C1041D-12 7C1041D-15  
Unit  
ns  
Maximum Access Time  
10  
80  
90  
10  
12  
75  
85  
10  
15  
70  
80  
10  
Maximum Operating Current  
Commercial  
mA  
Industrial  
MaximumCMOSStandbyCurrent  
Commercial/Industrial  
mA  
Note:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05472 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 29, 2005  
1234567...9

中文翻译

下载PDF

与CY7C1041D-15ZSXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1041DV33 CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041DV33_11 CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXIT CYPRESS

获取价格

 		Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 0.314 X 0.236 INCH, ROHS COMPLIANT, VFBGA-48
CY7C1041DV33-10BVXA CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXIT CYPRESS

获取价格

 		Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1041DV33-10VXC CYPRESS

获取价格

 		Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1041DV33-10VXI CYPRESS

获取价格

 		4-Mbit (256 K × 16) Static RAM

与CY7C1041D-15ZSXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证