Datasheet > CY7C1041DV33

CY7C1041DV33

更新时间： 2024-01-06 12:42:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	401K
描述
4-Mbit (256K x 16) Static RAM

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CY7C1041DV33 数据手册

CY7C1041DV33

4-Mbit (256K x 16) Static RAM

Features

Functional Description^[1]

• Pin- and function-compatible with CY7C1041CV33

• High speed

The CY7C1041DV33 is a high-performance CMOS Static

RAM organized as 256K words by 16 bits. Writing to the device

is accomplished by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then

data from I/O pins (I/O₀–I/O₇), is written into the location

specified on the address pins (A₀–A₁₇). If Byte HIGH Enable

(BHE) is LOW, then data from I/O pins (I/O₈–I/O₁₅) is written

into the location specified on the address pins (A₀–A₁₇).

— t_AA=10 ns

• Low active power

— I_CC= 90 mA @ 10 ns (Industrial)

• Low CMOS standby power

— I_SB2= 10 mA

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀– I/O₇. If Byte HIGH Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of Read and Write modes.

• 2.0 V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• Available in lead-free 48-ball VFBGA, 44-lead (400-mil)

Molded SOJ and 44-pin TSOP II packages

The input/output pins (I/O₀–I/O₁₅

)

are placed in

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1041DV33 is available in a standard 44-pin

400-mil-wide body width SOJ and 44-pin TSOP II package

with center power and ground (revolutionary) pinout, as well

as a 48-ball fine-pitch ball grid array (FBGA) package.

Logic Block Diagram

INPUT BUFFER

I/O –I/O

256K × 16

I/O –I/O

COLUMN

DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05473 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 17, 2006

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与CY7C1041DV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1041DV33_11	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVJXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 0.314 X 0.236 INCH, ROHS COMPLIANT, VFBGA-48
CY7C1041DV33-10BVXA	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1041DV33-10VXC	CYPRESS	获取价格	Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1041DV33-10VXI	CYPRESS	获取价格	4-Mbit (256 K × 16) Static RAM
CY7C1041DV33-10VXIT	CYPRESS	获取价格	暂无描述

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