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CY7C1041D-10VXI PDF预览

CY7C1041D-10VXI

更新时间: 2024-01-17 04:49:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 336K
描述
4-Mbit (256K x 16) Static RAM

CY7C1041D-10VXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSOP2, TSOP44,.46,32Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.8最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e4长度:18.415 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1.194 mm最大待机电流:0.01 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:10.16 mm

CY7C1041D-10VXI 数据手册

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CY7C1041D  
4-Mbit (256K x 16) Static RAM  
Features  
Functional Description[1]  
• Pin-and function-compatible with CY7C1041B  
• High speed  
— tAA = 10 ns  
The CY7C1041D is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. Writing to the device is  
accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A17).  
• Low active power  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• 2.0 V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
• Availableinlead-free44-Lead(400-Mil)MoldedSOJand  
44-Pin TSOP II packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1041D is available in  
a
standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Pin Configurations  
Logic Block Diagram  
/ TSOPII  
SOJ  
Top View  
INPUT BUFFER  
44  
1
A
A
17  
0
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
A
A
16  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
1
A
0
1
A
A
15  
2
A
A
OE  
3
A
2
3
BHE  
BLE  
A
I/O0–I/O7  
4
A
CE  
A
256K x 16  
4
I/O  
I/O  
0
15  
I/O8–I/O15  
A
5
6
I/O  
I/O  
I/O  
1
14  
13  
12  
A
I/O  
2
A
7
8
I/O  
V
I/O  
A
3
V
SS  
CC  
V
V
SS  
CC  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
9
8
COLUMN  
31  
30  
29  
28  
27  
26  
25  
I/O  
I/O  
I/O  
DECODER  
I/O  
I/O  
WE 17  
NC  
18  
A
A
14  
5
19  
BHE  
A
A
6
13  
WE  
CE  
OE  
A
20  
21  
22  
A
12  
11  
7
A
A
24  
23  
8
A
A
10  
9
BLE  
Note:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Document #: 38-05472 Rev. *C  
Revised March 31, 2006  
[+] Feedback  

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