Datasheet > 存储 > SRAM> CY7C1021CV33-8VXC

CY7C1021CV33-8VXC

更新时间： 2024-11-11 03:12:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	388K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021CV33

1-Mbit (64K x 16) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

The CY7C1021CV33 is a high-performance CMOS static

RAM organized as 65,536 words by 16 bits. This device has

an automatic power-down feature that significantly reduces

power consumption when deselected.

— Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

• Pin- and function-compatible with CY7C1021BV33

• High speed

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₁through I/O₈), is

written into the location specified on the address pins (A₀

through A₁₅). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₉through I/O₁₆) is written into the location

specified on the address pins (A₀through A₁₅).

— t_AA= 8 ns (Commercial & Industrial)

— t_AA= 12 ns (Automotive)

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₁to I/O₈. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₉to I/O₁₆. See

the truth table at the end of this data sheet for a complete

description of Read and Write modes.

• CMOS for optimum speed/power

• Low active power: 345 mW (max.)

• Automatic power-down when deselected

• Independent control of upper and lower bits

• Available in Pb-free and non Pb-free 44-pin 400-Mil SOJ

44-pin TSOP II and 48-ball FBGA packages

The input/output pins (I/O₁through I/O₁₆) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1021CV33 is available in 44-pin 400-Mil wide SOJ,

44-pin TSOP II and 48-ball FBGA packages.

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

64K x 16

A₄

I/O₁–I/O₈

RAM Array

A₃

A₂

A₁

A₀

I/O₉–I/O₁₆

COLUMN DECODER

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05132 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 6, 2006

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与CY7C1021CV33-8VXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021CV33-8VXCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1021CV33-8ZC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021CV33-8ZC	ROCHESTER	获取价格	Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, TSOP2-44
CY7C1021CV33-8ZCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, TSOP2-44
CY7C1021CV33-8ZXC	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV33-8ZXC	ROCHESTER	获取价格	64KX16 STANDARD SRAM, 8ns, PDSO44, LEAD FREE, TSOP2-44
CY7C1021CV33-8ZXCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021D	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D_11	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM CMOS for Optimu
CY7C1021D-10VXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM

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