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CY7C1021CV33-8VXCT PDF预览

CY7C1021CV33-8VXCT

更新时间： 2024-02-11 19:17:53
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 455K
描述
Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44

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CY7C1021CV33-8VXCT 技术参数

生命周期：Obsolete零件包装代码：SOJ
包装说明：SOJ,针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.38
最长访问时间：8 nsJESD-30 代码：R-PDSO-J44
JESD-609代码：e4长度：28.575 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX16封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：3.7592 mm
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：2.97 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：J BEND
端子节距：1.27 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY7C1021CV33-8VXCT 数据手册

 浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第2页浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第3页浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第4页浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第5页浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第6页浏览型号CY7C1021CV33-8VXCT的Datasheet PDF文件第7页 
CY7C1021CV33  
1-Mbit (64K x 16) Static RAM  
Features  
Functional Description  
■ Temperature ranges  
The CY7C1021CV33 is a high performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an  
automatic power down feature that significantly reduces power  
consumption when deselected.  
❐ Commercial: 0°C to 70°C  
❐ Industrial: –40°C to 85°C  
❐ Automotive-A: –40°C to 85°C  
❐ Automotive-E: –40°C to 125°C  
Writing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is  
LOW, then data from IO pins (IO1 through IO8), is written into the  
location specified on the address pins (A0 through A15). If Byte  
High Enable (BHE) is LOW, then data from IO pins (IO9 through  
IO16) is written into the location specified on the address pins (A0  
through A15).  
■ Pin and function compatible with CY7C1021BV33  
■ High speed  
❐ tAA = 8 ns (Commercial & Industrial)  
❐ tAA = 12 ns (Automotive-E)  
■ CMOS for optimum speed and power  
■ Low active power: 325 mW (max)  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on IO1 to IO8. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO9 to IO16. For more information, see the  
“Truth Table” on page 9 for a complete description of Read and  
Write modes.  
■ Automatic power down when deselected  
■ Independent control of upper and lower bits  
■ AvailableinPb-freeandnonPb-free44-pin400MilSOJ, 44-pin  
TSOP II and 48-Ball FBGA packages  
The input and output pins (IO1 through IO16) are placed in a high  
impedance state when the device is deselected (CE HIGH), the  
outputs are disabled (OE HIGH), the BHE and BLE are disabled  
(BHE, BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
64K x 16  
A4  
IO0–IO7  
RAM Array  
A3  
A2  
A1  
A0  
IO8–IO15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05132 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 11, 2007  
1234567...14

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CY7C1021CV33-8VXCT 替代型号

型号 品牌 替代类型 描述 数据表
IS61LV6416-8KL ISSI

功能相似

 IC SRAM 1M PARALLEL 44SOJ

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