Datasheet > CY7C1021CV26_05

CY7C1021CV26_05

更新时间： 2024-11-29 05:19:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	183K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021CV26_05 数据手册

CY7C1021CV26

1-Mbit (64K x 16) Static RAM

an automatic power-down feature that significantly reduces

power consumption when deselected.

Features

• Temperature Range

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₁through I/O₈), is

written into the location specified on the address pins (A₀

through A₁₅). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₉through I/O₁₆) is written into the location

specified on the address pins (A₀through A₁₅).

— Automotive: –40°C to 125°C

• High speed

— t_AA= 15 ns

• Optimized voltage range: 2.5V–2.7V

• Low active power: 360 mW (max.)

• Automatic power-down when deselected

• Independent control of upper and lower bits

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₁to I/O₈. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₉to I/O₁₆. See

the truth table at the end of this data sheet for a complete

description of Read and Write modes.

• Packages offered: 44-pin TSOP II and 44-Lead (400-Mil)

Molded SOJ

• Offered in both lead-free and non lead-free packages

The input/output pins (I/O₁through I/O₁₆) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

Functional Description

The CY7C1021CV26 is a high-performance CMOS static

RAM organized as 65,536 words by 16 bits. This device has

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

A₄

A₃

A₂

A₁

64K x 16

I/O₁–I/O₈

RAM Array

512 X 2048

I/O₉–I/O₁₆

A₀

COLUMN DECODER

BHE

BLE

Selection Guide^[1]

CY7C1021CV26-15

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Note:

1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V

, T = 25°C.

CC(typ.)

Cypress Semiconductor Corporation

Document #: 38-05589 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 7, 2005

12 3 4 5 6 7...9

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与CY7C1021CV26_05相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021CV26_10	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26_11	CYPRESS	获取价格	1-Mbit (64 K x 16) Static RAM CMOS for optimum speed/power
CY7C1021CV26-15BAE	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15BAET	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15VE	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV26-15VXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15VXET	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15ZE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15ZET	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, TSOP2-44
CY7C1021CV26-15ZSE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM

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