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CY7C1021CV33-10BAIT PDF预览

CY7C1021CV33-10BAIT

更新时间: 2024-11-21 21:08:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
13页 254K
描述
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48

CY7C1021CV33-10BAIT 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.09
最长访问时间:10 nsJESD-30 代码:S-PBGA-B48
长度:7 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:48
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:7 mmBase Number Matches:1

CY7C1021CV33-10BAIT 数据手册

 浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第2页浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第3页浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第4页浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第5页浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第6页浏览型号CY7C1021CV33-10BAIT的Datasheet PDF文件第7页 
CY7C1021CV33  
1-Mbit (64K x 16) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY7C1021CV33 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
• Pin- and function-compatible with CY7C1021BV33  
• High speed  
— tAA = 8 ns (Commercial & Industrial)  
— tAA = 12 ns (Automotive)  
• CMOS for optimum speed/power  
• Low active power: 360 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
• Also available in Lead-Free 44-pin TSOP II, 400-mil SOJ  
packages  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
The CY7C1021CV33 is available in standard 44-pin TSOP  
Type II, 400-mil-wide SOJ packages, as well as a 48-ball  
FBGA.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
7
6
5
4
64K x 16  
A
A
A
I/O –I/O  
RAM Array  
512 X 2048  
1
8
3
2
1
0
I/O –I/O  
9
16  
A
A
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05132 Rev. *E  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised March 7, 2005  

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