Datasheet > CY7C1021CV26_11

CY7C1021CV26_11

更新时间： 2024-11-27 09:43:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	528K
描述
1-Mbit (64 K x 16) Static RAM CMOS for optimum speed/power

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CY7C1021CV26_11 数据手册

CY7C1021CV26

1-Mbit (64 K × 16) Static RAM

1-Mbit (64

K × 16) Static RAM

automatic power-down feature that significantly reduces power

consumption when deselected.

Features

■ Temperature Range

❐ Automotive: –40 °C to 125 °C

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from I/O pins (I/O₀through I/O₇), is written into

the location specified on the address pins (A₀through A₁₅). If

Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈

through I/O₁₅) is written into the location specified on the address

pins (A₀through A₁₅).

■ High speed

❐ t_AA= 15 ns

■ Optimized voltage range: 2.5 V to 2.7 V

■ Low active power: 220 mW (Max)

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins will

appear on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then

data from memory will appear on I/O₈to I/O₁₅. See the truth table

at the end of this data sheet for a complete description of Read

and Write modes.

■ Automatic power-down when deselected

■ Independent control of upper and lower bits

■ CMOS for optimum speed/power

■ Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin

(400-Mil) Molded SOJ and Pb-free 48-ball FBGA packages

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a Write operation (CE

LOW, and WE LOW).

Functional Description

The CY7C1021CV26 is a high-performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

A₄

A₃

A₂

64 K × 16

I/O₀–I/O₇

RAM Array

I/O₈–I/O₁₅

A₁

A₀

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05589 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 20, 2011

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与CY7C1021CV26_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021CV26-15BAE	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15BAET	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15VE	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV26-15VXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15VXET	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM
CY7C1021CV26-15ZE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15ZET	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, TSOP2-44
CY7C1021CV26-15ZSE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15ZSXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV26-15ZSXET	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM

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