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CY7C1021CV26-15VXE PDF预览

CY7C1021CV26-15VXE

更新时间： 2024-10-01 05:19:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 183K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021CV26-15VXE 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOJ
包装说明：0.400 INCH, LEAD FREE, SOJ-44针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.23
Is Samacsys：N最长访问时间：15 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-J44
JESD-609代码：e4长度：28.575 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装等效代码：SOJ44,.44
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.6 V认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：3.7592 mm
最大待机电流：0.01 A最小待机电流：2.5 V
子类别：SRAMs最大压摆率：0.08 mA
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：2.6 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：J BEND
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：10.16 mm
Base Number Matches：1

CY7C1021CV26-15VXE 数据手册

 浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第2页浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第3页浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第4页浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第5页浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第6页浏览型号CY7C1021CV26-15VXE的Datasheet PDF文件第7页 
CY7C1021CV26  
1-Mbit (64K x 16) Static RAM  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
Features  
• Temperature Range  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
— Automotive: –40°C to 125°C  
• High speed  
— tAA = 15 ns  
• Optimized voltage range: 2.5V–2.7V  
• Low active power: 360 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
• Packages offered: 44-pin TSOP II and 44-Lead (400-Mil)  
Molded SOJ  
• Offered in both lead-free and non lead-free packages  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
Functional Description  
The CY7C1021CV26 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
64K x 16  
I/O1–I/O8  
RAM Array  
512 X 2048  
I/O9–I/O16  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Selection Guide[1]  
CY7C1021CV26-15  
Unit  
ns  
Maximum Access Time  
15  
80  
10  
Maximum Operating Current  
Maximum CMOS Standby Current  
Note:  
mA  
mA  
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
, T = 25°C.  
A
CC  
CC(typ.)  
Cypress Semiconductor Corporation  
Document #: 38-05589 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised March 7, 2005  
1234567...9

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